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Hardware Science Technology

16-Bit RISC-V Processor Made With Carbon Nanotubes (arstechnica.com) 50

Posted by BeauHD from the impressive-bit-of-engineering dept.
An anonymous reader quotes a report from Ars Technica: Now, researchers have used carbon nanotubes to make a general purpose, RISC-V-compliant processor that handles 32-bit instructions and does 16-bit memory addressing. Performance is nothing to write home about, but the processor successfully executed a variation of the traditional programming demo, "Hello world!" It's an impressive bit of work, but not all of the researchers' solutions are likely to lead to high-performance processors. The new processor was made by a collaboration between MIT researchers and scientists at Analog Devices, Inc., who figured out a way to work around all the issue with carbon nanotubes.

The key insight by the researchers behind the new chip was that certain logical functions are less sensitive to metallic nanotubes than others. So they modified an open source RISC design tool to take this information into account. The result was a chip design that had none of the gates that were most sensitive to metallic carbon nanotubes. The resulting chip, which the team is calling the RV16X-NANO, was designed to handle the 32-bit-long instructions of the RISC-V architecture. Memory addressing was limited to 16-bits, and the functional units include instruction fetching, decoding, registers, execution units, and write back to memory. Overall, over 14,000 individual transistors were used for the RV16X-NANO, and the manipulations of the carbon nanotubes to make them resulted in a 100% yield. In other words, every single one of those 14,000 gates worked. It was also what's considered a 3D chip, in that the metal contacts below the nanotube layer were used for routing signals among the different transistors, while a separate layer of metal contacts layered above the nanotubes was used to supply power within the chip. The report has been published in the journal Nature.
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16-Bit RISC-V Processor Made With Carbon Nanotubes More

16-Bit RISC-V Processor Made With Carbon Nanotubes

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  • So what's the benefit of nanotubes in computing if you can't use every Boolean? Runs cooler? More energy efficient? I don't see how either can be the case since that inevitably means you have to use more gates to do the same thing.

    • Re: (Score:1)

      by AHuxley ( 892839 )
      Gets funding next year.

      • We have a winner!

        This is why they made this, there is NO other reason.

    • Carbon nanotubes, it's what processors crave.

    • Re:Benefit? (Score:5, Informative)

      by EETech1 ( 1179269 ) on Thursday August 29, 2019 @01:39AM (#59135814)

      I believe there's a reduction in size, and an increase in frequency that's theorized. This is the first step in realizing it. The manufacturing is in its early stages, so this was the best they could do *for now* with the processes they had.
      That's why they chose to only use the specific gates that worked well with the limited ability they had to actually make the desired result.

      And as long as you get the desired output, does it really matter?
      The example given in the article is:

      It might be possible to add two numbers using the right arrangement of five ANDs and seven NORs, it could also be done with six NOTs and four NANDs. (Note: those numbers are completely made up.)

      Does it really matter what type of gates are used, when you get the correct result? Sure, it's a design limitation, but there are many.

      https://www.i-programmer.info/... [i-programmer.info]

      As a side note...
      How incredibly kick ass is it that an open source processor, with open source "easily modifiable" design tools, is a huge factor in enabling this work to happen!

      It will no doubt be aided by easily modified open source software for its runtime requirements as well.

      I read a lot about RISC-V, and it's very exciting to see everywhere it's going.

      • > Does it really matter what type of gates are used, when you get the correct result?

        Eventually, yes, because at a given feature size and wafer size you can only have so many transistors, so using the most efficient combinations of gates gets you more logic per chip and per dollar.

        At this point in the research it lets them work on other parts of the process whist not getting stuck on one gate type, so it's absolutely the right move for now.

        • so using the most efficient combinations of gates gets you more logic per chip and per dollar

          There's literally nothing wrong with your logic there. The issue is the process. I'm not into nanotubes so take my reply with a grain of salt, but if the process for nanotubes building up logic gates is significantly cheaper then you can use more gates and still fly under something like CMOS gate count for logic. For your statement there's the assumption that building up a gate in CMOS is equal to the cost it might be to do it in nanotubes, which may or may not be where it ultimately ends up.

          For the time

      • Re: (Score:2)

        by dargaud ( 518470 )

        It might be possible to add two numbers using the right arrangement of five ANDs and seven NORs, it could also be done with six NOTs and four NANDs. (Note: those numbers are completely made up.)

        It's 2 AND, 2 XOR and an OR gate for a full adder with a minimum of circuits.
        Or 9 NAND gates if you want to stick to those.

    • Runs cooler? More energy efficient?

      It's a new carbon sequestering scheme. Take carbon out of the air, and put it into carbon nanotube processors.

      Definitely worth an IgNobel.

    • Its probably worth noting as well that carbon nanotubes don't use rare earths, just boring old carbon thats everywhere. That means if we start hitting hard shortages, this stuffs in perpetually limited supply, we have options to keep making electronic *stuff*

      • Conventional semiconductors don't use any rare-earth elements in their construction. They're a baked silicon dioxide crust with boron, arsenic, or phosphorus doping.

        • Conventional semiconductors don't use any rare-earth elements in their construction. They're a baked silicon dioxide crust with boron, arsenic, or phosphorus doping.

          Traditional semiconductors require lots of nasty stuff though, from the Hydrofluoric acid to etch the wafers to the nearly-as-nasty solvents to grow the actual silicon crystals from. Rare earths aren't rare, and while surely not what the GP meant, the thing that makes rare earths so bad is all those same chemicals used to refine them (in about the same quantities.)

        • Conventional semiconductors use probably around 1/3 the periodic table today; they're far more complex than you make it seem.

      • That rare earth argument gets more and more boring. Just like mentioning thermodynamics.

        Basically every post containing either is: wrong

    • Are you afraid that more gates leads to less jobs?

    • Re: (Score:2)

      by gmack ( 197796 )
      The current Silicon based CPUs don't deal well with heat and radiation which makes their use problematic for space based applications.
    • In the early days of TTL (The days of Moon shots, and minicomputers) all gates* were built from NAND gates.

      * Obviously not Bill Gates

    • I think nanotubes can flex a lot more without becoming damaged. Once all the connections are made, you might be able to ditch the rigid substrate.

    • Re:Benefit? (Score:4, Insightful)

      by Richard Kirk ( 535523 ) on Thursday August 29, 2019 @01:18PM (#59137810)

      Silicon can be doped to make useful semiconductors. Silicon oxide is a good insulator. With these we can make circuits, but it has taken half a century to get this far.

      Carbon can be a super resistor, a resistor, a semiconductor, a conductor, and probably a superconductor without any other element, just by changing the bonds. If we could arrange the bonds just as we wanted them, we could have a mole of bytes in a few hundreds of grams of carbon. We might be able to trap flux quanta in pi orbital rings. All carbon circuits could be tremendous. But not yet. So far every carbon circuit has used a very high rejection ratio so we have one or two tubes in the right place to make a simple amplifier. And suddenly we have this. But it still isn't useful.

      There is a wire bonding technology that is used to get from the sub-micron scale of the silicon to the millimetre scale of the macro connections to a chip. If we are going to get to the molecular scale, then we are going to need an extra level of this sort of technology, to get from conventional microns to the nanometre scale of molecules. This is perhaps all we may get out of this. Early days, though.

    • To help aid into scientific discoveries, new methods in engineering and in manufacturing. Often we need to take a step back to see what we can do and what are the real issues with doing something. Back in the late 1990's there was a guy who made a web server powered by a potato. It was inferior to all other web servers. However such a study lets us learn with particular restrictions or with this new or different material at hand what can we do?

      We have been too jaded to marvel at novel idea or different a

  • 100% yield seems wrong. (Score:3)

    by shess ( 31691 ) on Thursday August 29, 2019 @12:25AM (#59135720) Homepage

    If I understand it right, they just randomly deposit stuff and then remove the things that aren't in the right place. Anyone can reach 100% yield if they are willing to measure after binning.

    • If I understand it right, they just randomly deposit stuff and then remove the things that aren't in the right place.

      That's how all semiconductor fabrication works: Photolithography [wikipedia.org].

    • No not everyone can reach that. If there are 14,000 transistors and a 0.995 success rate, they'd need not cpus than there are atoms in the earth to reach 100% yield.

    • Re: (Score:2)

      by AmiMoJo ( 196126 )

      Lithography, using light to remove material, is standard for the manufacture of both silicon chips and printed circuit boards. In fact a lot of manufacturing involves removing material, e.g. milling away metal or a sculptor chipping away rock.

      It's usually easier to remove material than to add it, because added material needs to be bonded somehow or it just falls off.

      • More precisely, lithography is the process of creating masks using light. Etching processes remove material (wherever the area isn't masked).

    • In actual high volume manufacturing, this is much harder than you describe. Being able to mask off nanometer features precisely, deposit films uniformly, etch out materials as intended, etc. are all huge efforts. Defects are everywhere and prevent yield (i.e. see Intel 10 nm troubles). There are 100s-1000s of steps to build the CPUs, if any one of them goes wrong, even in a tiny location on the chip, the whole CPU is bad. A modern CPU has billions of transistors and miles of interconnects, and everything ne

  • and does 16-bit memory addressing.

    Brings back memories. How about simulated 20 bit far pointers? Those were the days :)

  • How much power did this use ? (Score:4, Interesting)

    by Alain Williams ( 2972 ) <addw@phcomp.co.uk> on Thursday August 29, 2019 @03:02AM (#59135970) Homepage

    Carbon nano tubes can be made superconducting, so this could be great to use in huge data centres. A long way to go, but a great start!

    • Re: (Score:2)

      by AmiMoJo ( 196126 )

      We might finally get back to phones with batteries that last a week.

    • Superconducting properties is nice for interconnects, but for logic devices, they need to be semiconductors. You need to be able to turn them on/off.

  • Illustrated fabrication process diagram (Score:3)

    by Tetravus ( 79831 ) on Thursday August 29, 2019 @11:52AM (#59137332) Homepage
    Here's a detailed fabrication process diagram: https://www.nature.com/article... [nature.com] It's crazy that we can build stuff like this at scale... and amusing that the carbon nanotubes just look like random crosshatching in this diagram.

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