Intel Shows Off Work on Next-Gen Glass Core Substrates, Plans Deployment Later in Decade (anandtech.com) 3
Intel has showed off its initial work on developing a glass core substrate and associated packaging process for its chips. AnandTech: As a result of their progress with research and development on the class cores, Intel is now planning on introducing glass core substrates to its products in the second half of this decade, allowing them to package chips in more complex, and ultimately higher-performing configurations. There's a lot to unpack from Intel's relatively short announcement, but at a high level, glass core substrates have been under research for over a decade as a replacement for organic substrates, which are widely used in current-generation processors.
Essentially the medium that typical silicon dies sit on, substrates play an important part in chip packaging. First and foremost, they provide the structural stability for a chip (silicon dies are quite fragile and flimsy), and they are also the means through which signals from silicon dies are carried, either to other on-package dies (i.e. chiplets), or to the large number of relatively sizable pins/pads on the back side of a chip. And, as chip sizes have increased over the years -- and the number of pins/signals required by high-end chips has, as well -- so has the need for newer and better materials to use as a substrate, which is what's been driving Intel's latest accomplishment.
Essentially the medium that typical silicon dies sit on, substrates play an important part in chip packaging. First and foremost, they provide the structural stability for a chip (silicon dies are quite fragile and flimsy), and they are also the means through which signals from silicon dies are carried, either to other on-package dies (i.e. chiplets), or to the large number of relatively sizable pins/pads on the back side of a chip. And, as chip sizes have increased over the years -- and the number of pins/signals required by high-end chips has, as well -- so has the need for newer and better materials to use as a substrate, which is what's been driving Intel's latest accomplishment.
Crazy via pitch (Score:2)
TFA mentions that thru-substrate vias can be spaced every 100 microns. Not long before I got in the industry, that was the transistor gate dimension, not the dimension of a hole punched through the substrate. Wow.
Glass comes and goes. Wasn't there a move to glass platters for spinning disks in what, the late 90s? Whatever happened to that (other than the market getting crushed by SSDs)?
Re: (Score:1)
Sure you don't mean 100 nm, which was the gate dimension in the mid-late 90s? 100 um would be like 1960-1970s technology; about the width of a human hair.
Re: (Score:2)
Sure you don't mean 100 nm, which was the gate dimension in the mid-late 90s? 100 um would be like 1960-1970s technology; about the width of a human hair.
I'm crusty and old: I mean micrometer.
I'm actually fibbing a bit: the state of the art processor HP was producing when was hired there was a 10 micrometer NMOS chip. The prototype (the first PA-RISC system) was made with discrete logic chips. The first systems I used were Z-80 and 6502 based. I tried looking up the gate geometries of these and can't find them. 100 micrometer may be a bit of an overstatement.