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AI China Hardware

Chinese Researchers Used AI To Design RISC-V CPU In Under 5 Hours (tomshardware.com) 37

Posted by BeauHD from the performance-is-nothing-to-brag-about-though dept.
Required Snark shares a report from Tom's Hardware: A group of Chinese scientists has published (PDF) a paper titled "Pushing the Limits of Machine Design: Automated CPU Design with AI." The paper details the researchers' work in designing a new industrial-scale RISC-V CPU in under 5 hours. It is claimed this AI-automated feat was about 1000x faster than a human team could have finished a comparable CPU design. However, some may poke fun at the resulting AI-designed CPU performing approximately on par with an i486.

Training consisted of observing a series of CPU inputs and outputs. The scientists generated a Binary Speculation Diagram (BSD) from this I/O and leveraged principles of Monte Carlo-based expansion and Boolean functions to hone the accuracy and efficiency of the AI-based CPU design. Thus the CPU design was formed "from only external input-output observations instead of formal program code," explains the scientists. It also boasted an impressive 99.99999999999% accuracy. Using the above-outlined process, an automated AI design of a CPU was created.

The taped-out RISC-V32IA instruction set CPU was fabricated at 65nm and could run at up to 300 MHz. Running the Linux (kernel 5.15) operating system and SPEC CINT 2000 on the AI-generated CPU validated its functionality. In Drystone benchmarks, the AI-generated CPU performed on par with an i486. Interestingly, it appears to be a little bit faster than an Acorn Archimedes A3010 in the same test. Though some might be unimpressed by the performance of the AI-generated CPU, the scientists also seem quite proud that their generated BSD "discovered the von Neumann architecture from scratch."
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Chinese Researchers Used AI To Design RISC-V CPU In Under 5 Hours More

Chinese Researchers Used AI To Design RISC-V CPU In Under 5 Hours

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  • Its all fun and games... (Score:5, Insightful)

    by Rockoon ( 1252108 ) on Friday June 30, 2023 @08:04PM (#63647560)
    Its all fun and games until the transistors are so close together that arrangement actually matters.
    • Hmm, not sure for state of the art cpus, but for other stuff, the transistors for digital circuits are routed with place and route software. It is a rather ugly process.

    • Re: (Score:3)

      by stikves ( 127823 )

      That is where the iteration comes in.

      This model seems to have used an almost completely blind, black box architecture. It does not even know about the instruction, what is a register, or an arithmetic logic unit.

      Pass in designs for actual processors, and iterate the architecture to be able to handle sub-components, it might even come up with surprising results.

      And... it does not even need to do the entire design on its own. Coupled with a competent team, it can handle 80% of grunt work.

  • Umm, starting from a centralised external memory bus for large scale main memory kind of makes that the only architecture.

  • Did AI create an HDL description and then from that, floorplan and tape it up to be made into a set of masks? Doing that in 5 hours seems flat unbelievable. I might believe that the AI created an HDL description in 5 hours and that was fed into a traditional compiler and the output was used to load an FPGA.

  • just round one (Score:3)

    by metoc ( 224422 ) on Friday June 30, 2023 @10:09PM (#63647776)

    Imagine feeding western advanced chip design data (better than what the Chinese have) into something like GPT.

  • Damn impressive. (Score:5, Insightful)

    by dynamo ( 6127 ) on Friday June 30, 2023 @10:38PM (#63647826) Journal

    Creating a 486 from scratch, rather than going through iterative phases of design and learning from the previous design and so on, is fairly amazing for an early stage AI technology. When this gets good it will most definitely change how chips are designed - probably as an assistant to design subcomponents rather than as something that does entire chips, at least at first. In time, this is a basic step on the way to self-reproducing machines that can improve themselves. Beware.

    • NVIDIA already uses AI to improve the design of their own GPUs.

    • Only way to top that is Z-80 from scratch.

    • It also makes Independence Day a good deal more believable.

    • Re:Damn impressive. (Score:4, Insightful)

      by Waccoon ( 1186667 ) on Saturday July 01, 2023 @02:24AM (#63648048)

      Having skimmed through the PDF, it appears that the core is mostly based on lookup tables and uses AI to shorten the most probable paths. Impressive, but still very much a brute-force approach. The resulting core only supports the base integer instructions and is not pipelined, which explains why it's so large and slow. The die photo shows how huge the CPU core is compared to the Ethernet controller. Their technique reminds me of the logic compilers my dad used to use back in the 80's, but can handle way, way more inputs and outputs.

      Having dabbled in CPU design myself, it's actually not that hard to make a RISC core, as they rely only on a single opcode page. I'm actually not much of a fan of RISC-V since it really is a very simple and generic design. Trying to do the same thing with the x86 instruction set with nested opcode pages would be a LOT more impressive, but the resulting core would probably be huge and run like a slug.

      I'll have to take a closer look at this paper sometime.

    • Its a design that runs at 300mhz and performs a little better than the 12 mhz arm did.

    • In particular if you look at the ISPD (International Symposium on Physical Design) results from last year, AI-based chip design still has some way to go. In particular specialised tools like Cadence's CMP still easily beat throwing a *NN at it, and it's uncertain whether the latter will ever beat them since they're not really designed for this sort of thing.

      • It seems like the obvious thing to do is to make an AI that drives Cadence.

        It's senseless to just ignore the work humans have done to figure this stuff out when the software could be using the software.

    • This process didn't create a 486 from scratch. The reference to a 486 is for the performance comparison.

      The processor created was a RISC-V, i.e. the design process started with a pre-made ISA. Having to first create an ISA would have been a grad-school lab assignment 25 years ago; these days you'd do it in an undergraduate class.

  • Yeah, I'm not holding my breath (Score:3)

    by lsllll ( 830002 ) on Friday June 30, 2023 @11:05PM (#63647854)
    Good luck debugging that shit.

  • Can someone who knows a little of what they’re talking about comment on whether we could use this sort of process in an evolutionary form? Y’know like those genetic algorithms that run for a few thousand generations and end up with weird but functional designs?

    If it could be sped up and run thru that, we could get next gen processors in very short order.

    • Can someone who knows a little of what they’re talking about comment on whether we could use this sort of process in an evolutionary form?

      It seems the algorithm would have to be modified to allow for some randomness. Also, 5 hours is kind of slow for an evolutionary iteration (but that's not a deal-breaker if you're willing to throw money at it).

  • 300mhz performing like 12mhz arm (Score:3)

    by gl4ss ( 559668 ) on Saturday July 01, 2023 @05:00AM (#63648228) Homepage Journal

    Or a 33mhz 486 or something.

    300mhz 486 would fly. Though you could describe that as a pentium 2 or so.

    The acorn 3010 makes some sense for compare as its an arm, but it also ran at 12mhz, not 300, which is fairly important.

    • > acorn 3010 makes some sense for compare as its an arm Why? RISC-V isn't ARM. Do you mean because they are both RISC?
  • They used a machine to mash together a bunch of existing designs into one that performs much worse than any of the originals.

  • Much discussion about the implications for designing new CPU's etc, but how about figuring out how existing black boxes work? This research shows great potential for that.

    I'm thinking something like: hook up some black box IC to probes which register all its inputs & outputs, 'exercise' the equipment it's in by running a variety of tasks, and after enough rinse & repeat of that, have the AI spit out a rough model of the probed IC's function. Or start with die photo's of a decapped IC, and have an A

  • 4m gates is about 4 times more than what 486sx had. 486 used a feature size 12 times larger than this and RISC at this scale must have a substantial complexity advantage. A little surprised to find out Linux still works at all on computers without an FPU. Still for what it is quite interesting.

  • But wait until it designs RISC VI!
  • It's nothing new to add holistic algorithms in various EDA tools across design to TLM to RTL to MDP. AI is just the latest hammer in the toolbox looking for nails.

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