TSMC Wants To Unleash a Flood of Chiplet Designs With 3DFabric Alliance

An anonymous reader quotes a report from The Register: AMD turned to advanced packaging to create chiplet designs and become a formidable CPU player again. Apple used the tech to beef up the power of its M1 Ultra chip. And Intel is pinning its future success on 2D and 3D multi-die packaging technologies as part of its ambitious comeback plan. Now TSMC, the world's largest contract chipmaker, wants to make chiplet-based products easier and faster to manufacture using its growing toolbox of advanced packaging tech that has already benefited the likes of AMD, Apple, and others. The Taiwanese foundry giant plans to do this through the formation of the 3DFabric Alliance, announced Thursday, which aims to help chip designers implement advanced packaging tech into their plans faster by collaborating with partner companies that are key to the development process.

TSMC's partners cover several important elements of chip development, from electronic design automation and memory to substrates and testing. As part of the new alliance, they will have early access to TSMC's 3DFabric portfolio of 3D silicon stacking and advanced packaging technologies. The goal is to allow these partners to build new solutions in parallel with the development of TSMC's 3DFabric tech so that chip designers can get their hands on the tools, technologies, materials, and other resources necessary to make multi-die chip packages faster. TSMC's 3DFabric portfolio includes brand-new technology, like system-on-integrated-chips (SoIC), which underpins the 3D V-Cache tech in AMD's Milan-X and Ryzen 7 5800X3D processors that came out this year. The portfolio also includes older technologies: integrated-fan-out and chip-on-wafer-on-substrate (CoWoS), which have received new iterations over the past several years. Those using CoWoS include Nvidia and Amazon Web Services. Representatives from AMD, Nvidia, and AWS gave support for the new alliance, which is one of several set up by TSMC as part of its Open Innovation Platform initiative. TSMC veep of R&D, LC Lu, said while advanced packaging technologies can "open the door to a new era of chip-level and system-level innovation," "extensive ecosystem collaboration" is required to "help designers navigate the best path through the myriad options and approaches available to them."

"Through the collective leadership of TSMC and our ecosystem partners, our 3DFabric Alliance offers customers an easy and flexible way to unlocking the power of 3D [integrated circuits] in their designs," he added.

IOW

[drinkypoo]

Yields with larger dies are still terrible

Re:IOW

[ShanghaiBill]

Yields with larger dies are still terrible

Improving yields is a big advantage of chiplets.

Another advantage is using different processes for different chiplets. For instance, high-K semiconductors are a big benefit for DRAM. Special processes can also be used for I/O drivers, USB and Gigabit ethernet transceivers, etc.

Chiplets allow for more incremental and cost-effective designs than the traditional "tick-tock" (which is not working well for Intel). The chiplets can be individually improved step-by-step.

Re:

[DrMrLordX]

On which process?

Re:

[drinkypoo]

Presumably "5" and "7" nm both, but surely "5"

Re:

[DrMrLordX]

TSMC N7-family processes have phenomenal yields, and N5 is even better:

https://www.anandtech.com/show... [anandtech.com]

N7 at the very least has been used to yield relatively large dice, such as AMD's dGPU dice:

https://www.techpowerup.com/gp... [techpowerup.com]

(520mm2 isn't the largest die imaginable, but it's well north of the die size where you'd think "oh gee they're going to chiplets due to yield problems")

Re:

[tlhIngan]

Yields with larger dies are still terrible

Always has been.

Defects in silicon are basically spread all over the wafer. The larger the die, the greater the chance of hitting a defect, creating a dud chip. Larger dies also mean fewer chips per wafer, so the combination increases the cost exponentially.

Using smaller dies thus lowers the probability of a particular die landing on a defect area, and it increases the number of chips per wafer, which lowers the cost.

Large dies are only possible if you can put up wi

Interconnect is king

[JeffOwl]

Standardized interconnects between chiplets are key to making this really take off (Like AXI for FPGA IP cores). They have been trying for a while, but I think it was Intel who had the lead on low power high performance interconnect and was not willing to share under friendly terms. We have not reached the critical mass of chiplet variety and availability needed to make it economically viable. Hopefully that is coming.

No, AMD Dumped Bulldozer to Become Formidible

[BrendaEM]

Really, AMD regained their market by returning to a transitional CPU design. Yes, their chiplets an Infinity Fabric are part of the special sauce, but if they still used that special sauce with the Bulldozer/Piledriver, they would have been finished.