TSMC Reveals 2nm Node: 30% More Performance by 2025 (tomshardware.com) 56
Taiwan Semiconductor Manufacturing Co. today officially introduced its N2 (2nm class) manufacturing technology, its first node that will use gate-all-around field-effect transistors (GAAFETs), at its 2022 TSMC Technology Symposium. From a report: The new fabrication process will offer a full-now performance and power benefits, but when it comes to transistor density, it will barely impress in 2025 when it comes online. Being an all-new process technology platform, TSMC's N2 brings in two essential innovations: nanosheet transistors (which is what TSMC calls its GAAFETs) and backside power rail that both serve the same goal of increasing performance-per-watt characteristics of the node. GAA nanosheet transistors feature channels surrounded by gates on all four sides, which reduces leakage; furthermore, their channels can be widened to increase drive current and boost performance or shrunken to minimize power consumption and cost. To feed these nanosheet transistors with enough power and now waste any of it, TSMC's N2 uses backside power delivery, which the foundry considers to be among the best solutions to fight resistances in the back-end-of-line (BEOL).
Indeed, when it comes to performance and power consumption, TSMC's nanosheet-based N2 node can boast of a 10% to 15% higher performance at the same power and complexity as well as a 25% to 30% lower power consumption at the same frequency and transistor count when compared to TSMC's N3E. However, the new node increases chip density by only around 1.1X compared to N3E. In general, TSMC's N3 does offer full-node performance increases and power consumption reductions. But density-wise, the new technology can hardly impress. For example, TSMC's N3E node offers a 1.3X chip density increase over N5, which is a substantial increase.
Indeed, when it comes to performance and power consumption, TSMC's nanosheet-based N2 node can boast of a 10% to 15% higher performance at the same power and complexity as well as a 25% to 30% lower power consumption at the same frequency and transistor count when compared to TSMC's N3E. However, the new node increases chip density by only around 1.1X compared to N3E. In general, TSMC's N3 does offer full-node performance increases and power consumption reductions. But density-wise, the new technology can hardly impress. For example, TSMC's N3E node offers a 1.3X chip density increase over N5, which is a substantial increase.
Why are we still in nanometres? (Score:4, Insightful)
Why are we still in nanometres? I want single-digit ångströms, Å!
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Why are we still in nanometres? I want single-digit ångströms, Å!
See, this is a good example of how some people just settle for too little. I want to see a negative two nanometer process. That way the more electronic guts you have, the more extra space you get.
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Just name it 2 Planck lengths or something like that. And when you manage to get a "better" process, claim you're so good that you broke Planck units. That'll boost stocks! Perhaps.
Sarcasm aside, both the number and unit are mostly arbitrary these days, as they no longer refer to some actual physical properties of the manufacturing length that can be correlated with performance gains. So every fab uses different standards to derive those "labels" from.
There was an article on IEEE Spectrum
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I remember when 2 micrometers was small.
Of course, back then we didn't use photolithography masks, we used sharpies and magnifying glasses. Now get off my lawn.
Fake 2nm (Score:2)
How can it only be a 10% increase in transistor density? Something is being faked, something irrelevant measure, for marketing purposes. Not saying it didn't require genius level engineering to make it happen.
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Re:Fake 2nm (Score:5, Insightful)
Indeed. The same happened with FinFETs. You need space for the fins on two sides. With GAA, you have fins on all four sides. So even with smaller transistor feature sizes, the overall density isn't that much of an improvement.
The lower power consumption is the most important improvement, which is substantial. Longer battery life. Cooler datacenters.
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Re:Fake 2nm (Score:4, Funny)
Never heard of a dick measuring contest where the smallest wins. Is there any?
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Those were the days.
If it still fits in a pocket these days then it's much too small!
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Never heard of a dick measuring contest where the smallest wins. Is there any?
Feature size on silicon chips.
Re: Fake 2nm (Score:2)
There was one Howard Stern show that covered this. Unfortunately the IOC declined to pick-up the tiny baton.
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Probably a regular thing in China. That, and cartoon bear look-a-like contests.
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Let me guess, you're asking for a friend?
Re:Fake 2nm (Score:5, Informative)
Indeed
Nothing, absolutely nothing on the chip measures 2nm
A long time ago it measured the physical gate length of the transistors, but nowadays it's just the "equivalent gate length if they'd kept using the same MOS design". Which they haven't ;-)
Furthermore, the minimum pitch (distance between transistors) is often as important but seldom taken into consideration when discussing performance ...
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Can't be that, or the move from 3 to 2 nm would have resulted in more than a 10% increase in transistor density.
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The pitch is kept constant. Therefore the transistor density is the same.
However they must've slightly improved the FinFET topology hence the change to (psuedo) 2nm from (psuedo) 3nm
That is: faster transistors but the same density
Re: Fake 2nm (Score:2)
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They are physically smaller but need additional space around them, so all said and done density is the same but power consumption is lower. Better battery life, saving energy, cooler... Or run them faster.
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The idea is that this is "equivalnt to 2nm horisontally, but built vertically", while actual transistor is built vertically. This allows them to market it as "(equivalent to) x nm" without hitting the wall of quantum uncertainty principle, which is the insurmountable and starts at ~3nm because actual transistors are significantly larger than 3nm regardless of marketing wank involved.
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What is faked is your grasp of how semiconductor struture width is measured...
Re:Fake 2nm (Score:5, Informative)
TSMC doesn't use the terms "nanometer" or "nm" in any of their node names or descriptions. They switched to the 'N' series starting with N7. Common node families from TSMC are:
N7(N7, N7P, N7+, N6, possibly others)
N5 (N5P, N4, N4P, N4X)
N3 (N3, N3E, others)
etc.
This new node is N2. Not 2nm. The name implies that it has a 2nm feature size somewhere on a hypothetical SRAM test sell fabbed on N2, but the letters "nm" never actually appear in the name or in any media describing it.
Making sense of what these names really mean is difficult; for example, N7+ is more dense than N6 if I recall correctly.
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Wrong. N2 will be used in cell phone SoCs, GPUs, CPUs, APUs, etc.
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2nm. Ha ha, no really, how big is it? (Score:1)
Who cares? (Score:2)
Unless it's actually available for purchase, why should I give a damn just how small you can produce something?
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You can buy products using this process in 2025 or 2026. Patience. They haven't even rolled out N3-based products yet. The announcement is more for people in the semiconductor industry.
Re: Who cares? (Score:3)
If China invaded tiawan it would make the Ukraine eat look like a picnic. The Chinese are already working on decoupling thier economy from the rest of the world
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If you're not interested in future technology developments, why are you even here?
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Barely or Hardly? (Score:2)
Will it barely impress, or hardly impress? I was somehow left with both impressions after reading the article.
You know what impresses about the new density? TSMC's current process already has more of it than Intel's, and now their new process will have even more.
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The power usage on N2 looks very good. Density, not so much.
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The power usage on N2 looks very good. Density, not so much.
Well, it fails to hardly impress or whatever, it's not a big step forwards if that's what you mean. But it's still an improvement over already-beating-Intel...
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Node shrinks are getting really hard, and if Samsung continues to screw around, TSMC may be first to working GAAFETs. That alone is quite a step forward. Further refinements should improve density.
It will take more time and effort than ever to continue to improve performance from here on out.
The Patent (Score:3)
Gate-all-around field effect transistors with robust inner spacers and methods (https://patents.google.com/patent/US10903317B1/en)
The toms hardware story (Score:3)
Didn't have a diagram of the FETs this article is better: https://www.urduwebhub.com/202... [urduwebhub.com]
Intel 4 Info (Score:1)
https://www.realworldtech.com/... [realworldtech.com]
That's great but... (Score:2)
With TSMC putting all their efforts into the latest and greatest fab process, workhorse chip production is suffering. Older fab technologies still produce most of the non-sexy chips i.e. all of those small chips that populate a PCB near the main CPU. TSMC and others don't want to invest in new production lines for this stuff which ends up extending the overall component shortages everywhere. It'll take well into 2024 before things start to get back to normal. That's assuming that the demand stays static
Smaller feature size and larger transistors (Score:2)