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Hardware Technology

TSMC Reveals 2nm Node: 30% More Performance by 2025 (tomshardware.com) 56

Posted by msmash from the up-next dept.
Taiwan Semiconductor Manufacturing Co. today officially introduced its N2 (2nm class) manufacturing technology, its first node that will use gate-all-around field-effect transistors (GAAFETs), at its 2022 TSMC Technology Symposium. From a report: The new fabrication process will offer a full-now performance and power benefits, but when it comes to transistor density, it will barely impress in 2025 when it comes online. Being an all-new process technology platform, TSMC's N2 brings in two essential innovations: nanosheet transistors (which is what TSMC calls its GAAFETs) and backside power rail that both serve the same goal of increasing performance-per-watt characteristics of the node. GAA nanosheet transistors feature channels surrounded by gates on all four sides, which reduces leakage; furthermore, their channels can be widened to increase drive current and boost performance or shrunken to minimize power consumption and cost. To feed these nanosheet transistors with enough power and now waste any of it, TSMC's N2 uses backside power delivery, which the foundry considers to be among the best solutions to fight resistances in the back-end-of-line (BEOL).

Indeed, when it comes to performance and power consumption, TSMC's nanosheet-based N2 node can boast of a 10% to 15% higher performance at the same power and complexity as well as a 25% to 30% lower power consumption at the same frequency and transistor count when compared to TSMC's N3E. However, the new node increases chip density by only around 1.1X compared to N3E. In general, TSMC's N3 does offer full-node performance increases and power consumption reductions. But density-wise, the new technology can hardly impress. For example, TSMC's N3E node offers a 1.3X chip density increase over N5, which is a substantial increase.
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TSMC Reveals 2nm Node: 30% More Performance by 2025 More

TSMC Reveals 2nm Node: 30% More Performance by 2025

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  • Why are we still in nanometres? (Score:4, Insightful)

    by martinX ( 672498 ) on Friday June 17, 2022 @12:55AM (#62626982)

    Why are we still in nanometres? I want single-digit ångströms, Å!

    • Why are we still in nanometres? I want single-digit ångströms, Å!

      See, this is a good example of how some people just settle for too little. I want to see a negative two nanometer process. That way the more electronic guts you have, the more extra space you get.

    • Re: (Score:2)

      by fazig ( 2909523 )
      Yeah, why not?
      Just name it 2 Planck lengths or something like that. And when you manage to get a "better" process, claim you're so good that you broke Planck units. That'll boost stocks! Perhaps.

      Sarcasm aside, both the number and unit are mostly arbitrary these days, as they no longer refer to some actual physical properties of the manufacturing length that can be correlated with performance gains. So every fab uses different standards to derive those "labels" from.

      There was an article on IEEE Spectrum

    • I remember when 2 micrometers was small.

      Of course, back then we didn't use photolithography masks, we used sharpies and magnifying glasses. Now get off my lawn.

  • How can it only be a 10% increase in transistor density? Something is being faked, something irrelevant measure, for marketing purposes. Not saying it didn't require genius level engineering to make it happen.

    • I believe it's due to the increased complexity of transistors "gate-all-around field-effect transistors (GAAFETs)". So, while the feature size is much smaller, the overall size of each transistor is not much smaller. I'm guessing the complexity was required to reduce leakage and the previous iteration of transistors won't directly translate to functional CPUs on 2nm.

      • Re:Fake 2nm (Score:5, Insightful)

        by ShanghaiBill ( 739463 ) on Friday June 17, 2022 @03:22AM (#62627128)

        Indeed. The same happened with FinFETs. You need space for the fins on two sides. With GAA, you have fins on all four sides. So even with smaller transistor feature sizes, the overall density isn't that much of an improvement.

        The lower power consumption is the most important improvement, which is substantial. Longer battery life. Cooler datacenters.

    • nm measurement is purely a marketing term at this point, good example is AMD vs intel where intels higher nm process produces higher density of transistors than AMD's lower nm process. nm is a dick measuring marketing term only.

    • Re:Fake 2nm (Score:5, Informative)

      by usu4rio ( 1115041 ) on Friday June 17, 2022 @01:34AM (#62627026)

      Indeed

      Nothing, absolutely nothing on the chip measures 2nm

      A long time ago it measured the physical gate length of the transistors, but nowadays it's just the "equivalent gate length if they'd kept using the same MOS design". Which they haven't ;-)

      Furthermore, the minimum pitch (distance between transistors) is often as important but seldom taken into consideration when discussing performance ...

      • Re: (Score:3)

        by msauve ( 701917 )
        >nowadays it's just the "equivalent gate length if they'd kept using the same MOS design".

        Can't be that, or the move from 3 to 2 nm would have resulted in more than a 10% increase in transistor density.

        • The pitch is kept constant. Therefore the transistor density is the same.

          However they must've slightly improved the FinFET topology hence the change to (psuedo) 2nm from (psuedo) 3nm

          That is: faster transistors but the same density

          • its true you cant compare different companies versions of size, but you can accept that tsmc's 2mm is 30% faster and lower power than their 5nm, so its a better process and i'll probably update my non current gen amd 3900 for greater than 30% improvements when the chips land.

          • Re: (Score:2)

            by AmiMoJo ( 196126 )

            They are physically smaller but need additional space around them, so all said and done density is the same but power consumption is lower. Better battery life, saving energy, cooler... Or run them faster.

    • Re: (Score:2, Informative)

      by Luckyo ( 1726890 )

      The idea is that this is "equivalnt to 2nm horisontally, but built vertically", while actual transistor is built vertically. This allows them to market it as "(equivalent to) x nm" without hitting the wall of quantum uncertainty principle, which is the insurmountable and starts at ~3nm because actual transistors are significantly larger than 3nm regardless of marketing wank involved.

    • Re: (Score:2)

      by gweihir ( 88907 )

      What is faked is your grasp of how semiconductor struture width is measured...

    • Re:Fake 2nm (Score:5, Informative)

      by DrMrLordX ( 559371 ) on Friday June 17, 2022 @07:17AM (#62627418)

      TSMC doesn't use the terms "nanometer" or "nm" in any of their node names or descriptions. They switched to the 'N' series starting with N7. Common node families from TSMC are:

      N7(N7, N7P, N7+, N6, possibly others)
      N5 (N5P, N4, N4P, N4X)
      N3 (N3, N3E, others)
      etc.

      This new node is N2. Not 2nm. The name implies that it has a 2nm feature size somewhere on a hypothetical SRAM test sell fabbed on N2, but the letters "nm" never actually appear in the name or in any media describing it.

      Making sense of what these names really mean is difficult; for example, N7+ is more dense than N6 if I recall correctly.

  • Would someone more knowledgeable than myself describe the actual size of these features and how, other than "because marketing" they can be justified as 2nm equivalent? Are we 3-D stacking? What are the components of these transistors? How have they been changed?

  • Unless it's actually available for purchase, why should I give a damn just how small you can produce something?

  • Will it barely impress, or hardly impress? I was somehow left with both impressions after reading the article.

    You know what impresses about the new density? TSMC's current process already has more of it than Intel's, and now their new process will have even more.

    • The power usage on N2 looks very good. Density, not so much.

      • The power usage on N2 looks very good. Density, not so much.

        Well, it fails to hardly impress or whatever, it's not a big step forwards if that's what you mean. But it's still an improvement over already-beating-Intel...

        • Node shrinks are getting really hard, and if Samsung continues to screw around, TSMC may be first to working GAAFETs. That alone is quite a step forward. Further refinements should improve density.

          It will take more time and effort than ever to continue to improve performance from here on out.

  • The Patent (Score:3)

    by blahblahwoofwoof ( 2287010 ) on Friday June 17, 2022 @08:56AM (#62627708)

    Gate-all-around field effect transistors with robust inner spacers and methods (https://patents.google.com/patent/US10903317B1/en)

  • The toms hardware story (Score:3)

    by wakeboarder ( 2695839 ) on Friday June 17, 2022 @09:05AM (#62627730)

    Didn't have a diagram of the FETs this article is better: https://www.urduwebhub.com/202... [urduwebhub.com]

  • This guy writes very infrequently but excellently when he does so thought I'd add this fresh link.

    https://www.realworldtech.com/... [realworldtech.com]

  • With TSMC putting all their efforts into the latest and greatest fab process, workhorse chip production is suffering. Older fab technologies still produce most of the non-sexy chips i.e. all of those small chips that populate a PCB near the main CPU. TSMC and others don't want to invest in new production lines for this stuff which ends up extending the overall component shortages everywhere. It'll take well into 2024 before things start to get back to normal. That's assuming that the demand stays static

  • Definitely some good progress here but not the 16X density improvement over 8 nanometers that is implied by the headline.

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