Libre-SOC's Open Hardware 180nm ASIC Submitted To IMEC for Fabrication (openpowerfoundation.org) 38
"We're building a chip. A fast chip. A safe chip. A trusted chip," explains the web page at Libre-SOC.org. "A chip with lots of peripherals. And it's VPU. And it's a 3D GPU... Oh and here, have the source code."
And now there's big news, reports long-time Slashdot reader lkcl: Libre-SOC's entirely Libre 180nm ASIC, which can be replicated down to symbolic level GDS-II with no NDAs of any kind, has been submitted to IMEC for fabrication.
It is the first wholly-independent Power ISA ASIC outside of IBM to go Silicon in 12 years. Microwatt went to Skywater 130nm in March; however, it is also developed by IBM, as an exceptionally well-made Reference Design, which Libre-SOC used for verification.
Whilst it would seem that Libre-SOC is jumping on the chip-shortage era's innovation bandwagon, Libre-SOC has actually been in development for over three and a half years so far. It even pre-dates the OpenLane initiative, and has the same objectives: fully automated HDL to GDS-II, full transparency and auditability with Libre VLSI tools Coriolis2 and Libre Cell Libraries from Chips4Makers.
With €400,000 in funding from the NLNet Foundation [a long-standing non-profit supporting privacy, security, and the "open internet"], plus an application to NGI Pointer under consideration, the next steps are to continue development of Draft Cray-style Vectors (SVP64) to the already supercomputer-level Power ISA, under the watchful eye of the upcoming OpenPOWER ISA Workgroup.
And now there's big news, reports long-time Slashdot reader lkcl: Libre-SOC's entirely Libre 180nm ASIC, which can be replicated down to symbolic level GDS-II with no NDAs of any kind, has been submitted to IMEC for fabrication.
It is the first wholly-independent Power ISA ASIC outside of IBM to go Silicon in 12 years. Microwatt went to Skywater 130nm in March; however, it is also developed by IBM, as an exceptionally well-made Reference Design, which Libre-SOC used for verification.
Whilst it would seem that Libre-SOC is jumping on the chip-shortage era's innovation bandwagon, Libre-SOC has actually been in development for over three and a half years so far. It even pre-dates the OpenLane initiative, and has the same objectives: fully automated HDL to GDS-II, full transparency and auditability with Libre VLSI tools Coriolis2 and Libre Cell Libraries from Chips4Makers.
With €400,000 in funding from the NLNet Foundation [a long-standing non-profit supporting privacy, security, and the "open internet"], plus an application to NGI Pointer under consideration, the next steps are to continue development of Draft Cray-style Vectors (SVP64) to the already supercomputer-level Power ISA, under the watchful eye of the upcoming OpenPOWER ISA Workgroup.
Awesome (Score:4, Insightful)
This an excellent news and hearing this in our times we're living in right now feels like a gust of fresh air.
Looking forward to hear more from this.
Re:180 nm process tech is kinda old, no? (Score:4, Informative)
This is not about having the most powerful CPU.
Re: (Score:2)
Costs.
If for the same amount of money they received they could use a smaller lithography, I'm sure they would.
Why POWER? (Score:2)
Seriously, would not RISK-V have been the thing to go at this time, not some obscure, historical design?
Re: (Score:3)
Seriously, would not RISK-V have been the thing to go at this time, not some obscure, historical design?
They started with RISC-V, but latter on decided Power was more fitted to their project's goals because of "reasons".
Re: (Score:3)
Quoting the OpenPower Foundation page:
"“We developed this ASIC on the Power architecture because of its supercomputing pedigree, and the decades-long commitment and stability that IBM and other OpenPOWER Foundation members have sustained,” said Luke Kenneth Casson Leighton, lead developer and project coordinator for Libre-SOC. “On this strong base, we can build a reliable, efficient Hybrid 3D CPU-VPU-GPU, and our next test ASIC will include Draft Cray-style Vector Extensions, SVP64.”
Re: (Score:1)
Sounds like "IBM did bribe and coerce us to do it"....
Re:Why POWER? (Score:5, Informative)
Sounds like "IBM did bribe and coerce us to do it"....
no, the OPF (not IBM) asked me to do a nice quote, of course i laid it on thick with a 24-in trowel :) but seriously: (a) we don't have any direct sponsorship or relationship with IBM and (b) i wouldn't say something like that if i didn't actually believe it.
Re: (Score:2)
Probably because RISC-V is getting some wealthy backers and this device, which is being fabricated an old technology node would simply be an un-competitive curiosity when compared to other RISC-V offerings.
Re: (Score:1)
historical? obscure?
power is current, and has richer instruction set than RISC V. seems better choice for high performance computing
Re: (Score:2)
This thing is not aimed at "high performance computing". Manufacturing it in 180nm should make that amply clear....
Re:Why POWER? (Score:5, Informative)
This thing is not aimed at "high performance computing". Manufacturing it in 180nm should make that amply clear....
correct. it's a test chip, aimed at helping the team to understand and appreciate the complexities of doing an ASIC *at all*. if it executes anything, even just one or two instructions, that's a resounding success.
Re: (Score:2)
One does not simply fabricate on one node then move it over to another by simply recompiling. If you get it fabbed at 180nm, you only proved you made it work at 180nm. You don't take that go to a 90nm fab and have them make the same thing - it just doesn't work that way. You have to get new design
Re: (Score:1)
The post I was replying to said:
"would not RISK-V have been the thing to go at this time, not some obscure, historical design?"
The answer is no, Power is a superior design and instruction set, at any node size.
Re: (Score:1)
Re: (Score:2)
IBM chose to serve a very particular customer base, one with deep pockets and a need for high performance I/O. it's always been the case that IBM POWER processors have more than double the I/O throughput and memory bandwidth compared to similar "performing" (raw computational) x86 processors. it's not a coincidence therefore that of the top500 supercomputers, POWER9 systems are 2nd and 3rd at the top of that list.
however very interestingly this leaves a gaping hole in the market for something that leverag
Re:Why POWER? (Score:5, Informative)
I disagree with the assertion that POWER is an obscure design, nor an historical one.
It is not obscure for people familiar with CPU architectures, MacIntoshes, Be OS, etc...
And POWER in its POWER 9 incarnation is nothing historical, see some comparisons with ARM, EPYC, XEONS:
https://www.phoronix.com/scan.... [phoronix.com]
https://www.phoronix.com/scan.... [phoronix.com]
Re: (Score:2)
Wasn't POWER the base unit of the PS3 Cell processor? I could see a fully open CPU/GPU combo that lends itself to scaling outward like that having an *enormous* amount of potential. Particularly if layout was done with miniaturization in mind e.g. if once they've got a 180nm processor working reliably they could fairly easily move to 18nm for a 10x10 100-multicore array in the same wafer footprint.
Re: (Score:2)
PowerPC, as with earlier versions of Xbox and Wii before each console switched to x86_64. As found in Macintoshes, an older version of the ISA which followed a different line of evolution from IBM's current day server chips.
But the magic of Cell was in the proprietary co-processors which weren't part of PowerPC/Power and hence unavailable for this project.
Re: (Score:2)
Both PS3 and Xbox 360 used PowerPC cores. Cell had a lot more to it, though.
Re:Why POWER? (Score:5, Informative)
Seriously, would not RISK-V have been the thing to go at this time
this post - which is the best of many excellent pieces of analysis - says it all: https://news.ycombinator.com/i... [ycombinator.com]
the biggest giveaway:
RISC-V is however a special case. Even if I have never spent time with implementing any program for it, after having experience with assembly programming for more than a dozen ISAs, when I see that almost any RISC-V loop may require up to a double number of instructions compared to most other ISAs, then I do not need more investigations to realize that reaching the same level of performance with RISC-V will require more complex hardware than for other ISAs.
in a discussion on the libre-soc-dev mailing list you can find the paper by the alibaba group: http://lists.libre-soc.org/pip... [libre-soc.org]
the team had to add custom LOAD/STORE modes that are entirely missing from RISC-V:
First, we support register + register addressing mode, and
support indexed load and store instructions. This type of
instruction extension reduces the usage of the registers for
calculation and reduces the number of instructions for address
generation, thereby effectively accelerating the data access
of a loop body. Second, unsigned extension during address
generation is supported. Otherwise, the basic instruction set
does not support direct unsigned extension from 32-bit data
to 64-bit data, resulting in too many shift instructions.
adrian_b in the ycombinator post explains that the assumption "there's always compressed which makes things smaller" is bogus, because it massively complicates the decode and issue phase. whilst this is fine for simple designs if you want to go massive-wide multi-issue (8, as is done in IBM POWER10 and the M1), you've got a serious problem.
bottom line is that RISC-V is wholly unsuited to supercomputing tasks.
Re: (Score:2)
Or, to put it more directly, RISC was a failed experiment. As it turns out, CISC ISAs *are* more capable than RISC ones. Of course, most RISC players learned this in the 80s and evolved their ISAs to not be so "Reduced". Here is an example where a vestigial true RISC ISA is exposed as simply not competitive.
This is great news.... (Score:4, Insightful)
Now that the x86 monopoly (on desktops and servers) is breaking down, it's fantastic to see a proliferation of CPU options that are open source, saving everyone money compared to the inflated Intel/AMD pricing enabled by their monopoly leverage. Perhaps only Apple had the leverage and the guts to take on Intel at scale, but now that they've proved the point that non-x86 price/performance lags, so it's creating the opportunity for these open source chip designs that have been underway for years to get real traction.
And PowerPC in particular is a very mature high performance computing platform, so if there's an open source PPC chip option, that's fantastic for high performance computing expand past IBM's PPC server market. And since they're all linux-based dev platforms, where cross-compilers proliferate (e.g. http://kernel.c3sl.ufpr.br/pub... [c3sl.ufpr.br] ) portable apps should run on all these CPUs fairly easily. The client-side is a bit more fragmented, with Windows, Android, MacOS, iOS, etc., but these days they're more portable too, though they're controlled by companies that would need to decide to support the various chips. But even then, it means that (for example) MS or Google aren't trapped by x86 any more, so if these newer options are better price performance, they can adopt them and benefit everyone (other than Intel and AMD) by improving price/performance.
Re: (Score:1)
Apple is shooting themselves in the foot. They used to be a very open company - providing schematic diagrams for their computers and peripherals, assembly code for their firmware, and tech notes with very low-level examples - but are becoming excessively insular and secretive as they progress. Now that they're using their own processor designs in desktop, laptop and mobile they're a gated technology island and they have a real and high risk of pissing off (all) software developers and finding themselves wit
Re: (Score:2)
Is this a troll?
Re: (Score:2)
Teaching China ASIC tech for free (Score:2)
Stop that.
Re: (Score:3, Informative)
Stop that.
they already know how - and can do it better than the West, anyway.
Chinese state-backed chip designer Loongson eyes $0.5bn Shanghai IPO
https://www.verdict.co.uk/chin... [verdict.co.uk]
Re: (Score:2)
Yes, Longsoon makes the best ASICs!!!!
Oh wait, no they don't.
Re: Teaching China ASIC tech for free (Score:1)
Go away. These efforts benefit the whole world not just people you approve of.
I feel like.. (Score:1)
Awesome, But 180 Nanometers? (Score:2)
Re: (Score:3)
it's a test chip, which helps prove that the team can actually develop silicon *at all*, at a low MPW cost of only EUR 20,000. costs double from there: MPW Programs for 28nm start at around USD 100,000, 14nm will be USD 200k, and so on.
now that we've done a MPW that only cost EUR 20,000 we can move to lower geometries with less risk of a costly error.