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Hardware

MIT Unveils the World's Most Advance Carbon Nanotube Chip (technologyreview.com) 37

"A team of academics at MIT has unveiled the world's most advanced chip yet that's made from carbon nanotubes," reports MIT's Technology Review: Not only are nanotube transistors faster than silicon ones, studies have found that chips made from nanotubes could be up to ten times more energy efficient. This efficiency boost could significantly extend electronic gadgets' battery life. Researchers have been working on alternative chips involving the molecules for decades, but manufacturing headaches have kept the processors stuck in research labs. In a paper published in Nature, the MIT team says it has found ways to overcome some of the biggest hurdles to producing them at scale...

[C]hallenges intrigued Max Shulaker, an MIT professor who has worked on other notable projects in the field, and has received funding from the US Defense Advanced Projects Research Agency to develop nanotube technology. The group of researchers he leads has developed a working 16-bit microprocessor [based on the RISC-V instruction set and running standard 32-bit instructions] built from over 14,000 carbon nanotube transistors that Shulaker claims is the most complex ever demonstrated. The techniques they have come up with can be implemented with equipment used for making conventional silicon chips, which means chipmakers won't have to invest in expensive new gear if they want to make nanotube processors...

Researchers discovered that some kinds of logic gates, which are fundamental building blocks of digital circuits, were more resistant to problems triggered by metallic-like nanotubes than others. That led them to develop a new circuit design that prioritizes these gates, while minimizing the use of more sensitive metallic ones... The chip that the MIT researchers produced using these techniques is capable of running a simple program that produces the message "Hello, World."

Shulaker says the significance of their research is it clearly points the way for a transition from silicon to carbon nanotubes. "There's no leap of faith required anymore."
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MIT Unveils the World's Most Advance Carbon Nanotube Chip

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  • The highest transistor count to date is ~+15,000,000,000. With the average cpu clock cycle being around 3GHz we have 3B operations per second. I ask that when they have a full fledged carbon nanotube cpu for my nav computer, can I do the Kessel run in less than 12parsecs? Asking for a friend.
    • The article doesn't say they are the most complex chips (like the summary says), it says they are the most complex carbon nanotube chips.
      • The article doesn't say they are the most complex chips (like the summary says), it says they are the most complex carbon nanotube chips.

        Exactly. TFS goes all "click-bait-y" implying much more than TFA actually puts forward.

        There will still need to be large improvements across a number of different areas/parameters regarding CN chips from manufacturing efficiencies & processes to cost/performance, power efficiency, packaging & standardization, etc, and total carbon footprint plus other environmental concerns before they'll be replacing silicon in any large numbers.

        You're not going to be seeing Intel or AMD rolling out CN-chip-based

  • Huh? (Score:3, Interesting)

    by topham ( 32406 ) on Monday September 16, 2019 @12:14AM (#59198130) Homepage

    You don't make a chip that can say Hello World. You make a chip that can do anything.

    You write a program to run on it that says "Hello World"; to announce itself to the universe.

  • Once you make the switch to carbon nanotubes, is there a dimension for improvement analogous to silicon transistor feature size?
    • by AHuxley ( 892839 )
      Make it smaller and smaller.
      Until the billions in new investment of US$ needed to work around the quantum effects. Does it fail?
      Then try something new again.
      Only billions in new investment will really find out if it will not work.
      Keep on investing until the full quantum effects cant be worked around.
      Add more math to look for errors during usage and allow for lots of expected quantum effects?
      Then try something new again.....
      • Make it smaller and smaller.

        You can't make them smaller, but you can go 3D, and stack them in layers.

        The challenge will be getting the heat out of the inner layers.

        • by AHuxley ( 892839 )
          Is the 3D stack worth the effort and investment then?
        • Make it smaller and smaller.

          You can't make them smaller, but you can go 3D, and stack them in layers.

          The challenge will be getting the heat out of the inner layers.

          How about stacking them into interesting shapes?

          • by AHuxley ( 892839 )
            Re 'How about stacking them into interesting shapes?"
            A 3D cheetah image? A whale? Muscleman? A penguin?
            • Re 'How about stacking them into interesting shapes?"

              A 3D cheetah image? A whale? Muscleman? A penguin?

              Now you're getting it. The sky is the limit ;)

        • The interconnects between the components become a problem, you have to cross-connect somehow, and it's difficult to put down layers to keep the connections aligned or to drill down somehow to connect leyers. And there is no such thing as a "3D ground plane" to help isolate signals and reduce excessive ground bounce among distinct components. The current in such a ground plane, or power plane, would inevitably wind up traveling in loops that _will_ couple magnetically to sensitive signals. I also wish you lu

          • In principle, simulation software can identify coupling and bounce and synchronization problems. If ever written, expect such software to be expensive, buggy, and very very slow.

            In practice, who knows? Perhaps 3D design will involve "good design practices" and decreasing the clock speed until the circuit works.

            Some interconnect problems can be fixed with differential signals, although there's a power penalty doing that. Optical interconnection also fixes some interconnect problems, but that's nowhere near p

            • In principle, simulation software can identify coupling and bounce and synchronization problems.

              The kinds of algorithms that do these sorts of things tend to be very slow asymptotically speaking, and the data input N on modern chips tends to be rather high.

    • Moore's law is almost as frequently misunderstood as Murphy's law.

      It is about gate count, not about die size, or feature size.

      As such, no analogous feature is needed. We can use the exact same metric.

    • Once you make the switch to carbon nanotubes, is there a dimension for improvement analogous to silicon transistor feature size?

      Well a good way to think about this is to first think about why we make transistors smaller to begin with. We make transistors smaller to pack more into a smaller package. There's a lot of pros and cons to doing that, which I'm sure that the more pedantic folks of Slashdot will be able to fill you in on the ones I miss here. The two I'll focus on is energy consumption and speed. Imagine a unit of length measurement. Okay, great, I'll just refer to that as a unit.

      So consumption wise, for every unit of l

      • Active logic gates have voltage gain. Each time a signal that's been degraded by distance goes through an active logic gate, it's squared up again to some degree.
  • by io333 ( 574963 ) on Monday September 16, 2019 @02:10AM (#59198236)

    It's the next GREAT THING.

    I've been waiting 40 years.

    Where is it!

    (wake me up if I'm still alive when I can have my 10x faster A117 carbon nanoprocessor in my implanted iBrain)

  • by PolygamousRanchKid ( 1290638 ) on Monday September 16, 2019 @03:10AM (#59198316)
    1. Ban silicon in all chips. Only allow carbon tube chips.
    2. Force chip manufacturers to use sequestered carbon from the air.
    3. Bury the chips when they die.
    4. Climate change is fixed!

    . . . and the Internet is just a series of tubes anyway, so using chips of tubes is a good plumbing fit.

  • by cb88 ( 1410145 ) on Monday September 16, 2019 @10:12AM (#59199354)
    Arstechnica ran an *actual* article on this last month. In short this isn't a usable technology just a stepping stone along the way, it runs at kilohertz, and isn't efficiency due to having a non ideal layout caused by the method of organizing the nanotubes. It took them 10 years of research to go from ~150 transistors to ~14000 transistors. If that rate continues it could be usable in some exotic use cases in a few years.... perhaps high temp etc...
    https://arstechnica.com/science/2019/08/16-bit-risc-v-processor-made-with-carbon-nanutubes/
    • t took them 10 years of research to go from ~150 transistors to ~14000 transistors. If that rate continues it could be usable in some exotic use cases in a few years.... perhaps high temp etc..

      Hmm. 10 years... 150 to 14,000...

      2**n = 14000 / 150
      ln (2**n) = ln (14000 / 150)
      n = ln (14000 / 150) / ln (2)
      n = ~6.5

      About 6.5 doublings in 10 years. That's 10 / 6.5 = 1.5 years per doubling. A bit faster than Moore's Law, but in the same ballpark.

  • We already know many of the miracle properties of new metamaterials. The problem with what seems like monthly revolutionary processor claims using graphene, carbon nanotubes, yada yada... without the mass production scale and cheap pricing of silicon they will be limited to niche markets and research projects.. Someone affordably mass produced chips using a metamaterial other than silicon is where the real revolutionary breakthrough needs to happen.

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