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Software Hardware Technology

PCI Express 5.0 Announced With 32GT/s Transfer Rates (phoronix.com) 62

The Peripheral Component Interconnect Special Interest Group (PCI-SIG) today announced PCI Express 5.0, even though PCI Express 4.0 is still a rarity in the PC market. Phoronix reports: PCI Express 5.0 doubles the bandwidth of PCIe 4.0 with a promise of 32GT/s transfer rates while maintaining low-power and backwards compatibility with existing PCI Express specifications. PCI Express 5.0 is set to allow 128GB/s bandwidth via PCIe 5.0 x16, improved signal integrity and mechanical performance, a new "CEM" connector for add-in cards, and backwards compatibility back through PCIe 1.x. Additional details can be found via today's PCI-SIG press release.
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PCI Express 5.0 Announced With 32GT/s Transfer Rates

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  • now what about boards with x16 x16 switched from X16. PCI-4 or 5 x8 x8 is not that good on gen 3 cards. But with an switch one X16 bus can drive 2 gen3 slots at full X16.

  • by mentil ( 1748130 ) on Wednesday May 29, 2019 @10:19PM (#58676604)

    Intel has plans to release chips with support for PCIe 5.0 in 2021, apparently skipping PCIe 4.0. AFAIK it's unknown when AMD will support PCIe 5.0, although PCIe 4.0 support is coming with this year's AMD chips/mobos. I expect a Zen 2+ microarch from AMD next year, with a Zen 3 in 2021 that also supports PCIe 5.0.

    • It's 3 years minimum till hardware lands going by all the past standards. Intel will do 4.0 just like AMD for the next 3 years then upgrade just like AMD will.

      • by mentil ( 1748130 )

        PCIe 4.0 had its final revision released 2 years ago, and this year we're getting hardware. Intel is doing PCIe 4.0 for its FPGAs and some similar products. I meant for its desktop x86 CPUs.

    • by AmiMoJo ( 196126 )

      It will be very interesting to see how much benefit PCIe 4.0 brings. Intel must think it won't be much if they are willing to concede that ground for a whole year.

  • by rahvin112 ( 446269 ) on Wednesday May 29, 2019 @10:31PM (#58676636)

    Following in the footsteps of all PCIe standards now that it's standard it will be 3-4 years before the first hardware lands.

    • It does take some time to develop hardware once a standard is set. Having worked on high speed buses, its hard(tm). Someone needs to make silicon, then high speed boards / connectors, etc etc.

    • That's neither weird nor a problem. Its actually very common in engineering. You have to set the standard first before hardware the conforms to the standard can be produced and fabbing new silicon designs takes time as well. Then of course there is validating everything and getting it in products and on the shelf. Each of those is a complicated multi-step process. 3-4 years between when a new standard is ratified and you see it in consumer products is the norm.

    • by MrL0G1C ( 867445 )

      That not what I've heard, AMD X570 chipset supports PCIe 4.0 (coming out July) and there's already talk of SSDs that will support it for faster transfers.

  • by Orgasmatron ( 8103 ) on Wednesday May 29, 2019 @11:15PM (#58676878)

    In case anyone was wondering, the new CEM connector is the "slot" soldered to the motherboard. It looks pretty much identical to the past generations, which shouldn't be a surprise to anyone because it still accepts old PCIe cards back to the first generation.

    According to Amphenol [amphenol-icc.com]:

    The PCIe Gen 5 channel data-rate of 32GT/s requires a better mating connector, an AIC with improved PCB material, optimized vias, and alternative trace routings. The Gen 5 surface-mount connector mates with the smaller gold edge fingers with a shorter wipe distance to achieve loss and crosstalk targets at twice the Gen 4 Nyquist frequency. AIC microstrip or stripline routings, via choices, ac capacitor mounting, and their effects are optimized for overall channel performance. AIC lead-in trace region to the connector is re-designed to improve the impedance match to the CEM connector. Measurements of a connector prototype with improved AIC validate the work.

    • by Anonymous Coward

      happen.

      There is a reason connectors have remained through hole even while every other component on the board has become SMT. The structural integrity simply isn't there. Unless they have improved through hole tabs soldered on to hold the connector in place (and even then I have reservations...) this is just going to end up with more motherboards becoming junk a lot faster as a result of flexing pulling up the SMT pins, or worse yet delaminating the contacts/traces from the board, either of which will effect

      • Re: (Score:3, Informative)

        by Anonymous Coward

        The cost of a 400x Digital USB microscope is about $30 on eBay.
        The cost of a cheap computer with an 1920x1080 screen is about ... well just pull one out of the trash
        The cost of a soldering iron with a tip fine enough to lift even the smallest capacitors is about $25 (though the $100 model is worth it), you need two of them.
        The cost of a great set of tweezers is maybe $20.
        Then there's resin, alcohol wash, super-thin solder.

        I would also recommend buying a cheap CoreXY based CNC laser from china (about $50-$10

    • by Agripa ( 139780 )

      In case anyone was wondering, the new CEM connector is the "slot" soldered to the motherboard. It looks pretty much identical to the past generations, which shouldn't be a surprise to anyone because it still accepts old PCIe cards back to the first generation.

      According to Amphenol [amphenol-icc.com]:

      The PCIe Gen 5 channel data-rate of 32GT/s requires a better mating connector, an AIC with improved PCB material, optimized vias, and alternative trace routings. The Gen 5 surface-mount connector mates with the smaller gold edge fingers with a shorter wipe distance to achieve loss and crosstalk targets at twice the Gen 4 Nyquist frequency. AIC microstrip or stripline routings, via choices, ac capacitor mounting, and their effects are optimized for overall channel performance. AIC lead-in trace region to the connector is re-designed to improve the impedance match to the CEM connector. Measurements of a connector prototype with improved AIC validate the work.

      So they reinvented what was done 40 years ago. Well done.

      Obscure? Electronic Design, Volume 27, January 18, 1979.

  • Do we really need to obsolete all of our stuff for an incremental gain in performance?

Every nonzero finite dimensional inner product space has an orthonormal basis. It makes sense, when you don't think about it.

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