Japan's Fujitsu and RIKEN Have Dropped the SPARC Processor in Favor of an ARM Design Chip Scaled Up For Supercomputer Performance (ieee.org) 40
Japan's computer giant Fujitsu and RIKEN, the country's largest research institute, have begun field-testing a prototype CPU for a next-generation supercomputer they believe will take the country back to the leading position in global rankings of supercomputer might. From a report: The next-generation machine, dubbed the Post-K supercomputer, follows the two collaborators' development of the 8 petaflops K supercomputer that commenced operations for RIKEN in 2012, and which has since been upgraded to 11 petaflops in application processing speed. Now the aim is to "create the world's highest performing supercomputer," with "up to one hundred times the application execution performance of the K computer," Fujitsu declared in a press release on 21 June. The plan is to install the souped-up machine at the government-affiliated RIKEN around 2021. If the partners achieve those execution speeds, that would place the Post-K machine in exascale territory (one exaflops being a billion billion floating point operations a second). To do this, they have replaced the SPARC64 VIIIfx CPU powering the K computer with the Arm8A-SVE (Scalable Vector Extension) 512-bit architecture that's been enhanced for supercomputer use, and which both Fujitsu and RIKEN had a hand in developing. The new design runs on CPUs with 48 cores plus 2 assistant cores for the computational nodes, and with 48 cores plus 4 assistant cores for the I/O and computational nodes. The system structure uses 1 CPU per node, and 384 nodes make up one rack.
Re: Yes but (Score:2)
No
Can we please stop with this outdated joke? (Score:2)
Nothing can run Crysis.
Fujitsu SPARC M3000 & Solaris 10 (Score:2)
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SVE is a flexible in terms of vector length, with maximum width of 2048 bits. The 512 was likely selected due to power, bandwidth and chip real-estate reasons. We should know more after the Hot Chip representation, available free for everybody at this December the latest.
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"SVE is a flexible in terms of vector length, with maximum width of 2048 bits."
AVX can get wider too if it makes sense. The fact that an exotic purpose-built supercomputer chip that won't be in real operation until 2021 is clearly taking design cues from a 2017-era consumer-grade part that you can use to play video games kind of shows how this nonsense about "ARM" vs. "x86" doesn't mean anything in the real world.
Incidentally, for all the crap about "RISC" that gets tossed around here like a magic get-out-o
Re:512 bits eh? (Score:5, Insightful)
"anybody who actually knows what RISC actually means would tell you that any and all SIMD units violate RISC's principles."
No, SIMD units do not "violate RISC's principles" and your saying so only demonstrates your own shallow understanding of what these principles are. RISC may mean "reduced instruction set computing" but that doesn't mean the end game is the smallest instruction set.
RISC is about making an architecture that is easy to implement by eliminating instructions that aren't needed for good performance. In doing this, designers can spend their gates on performance wins rather than on logic that can just as easily be reproduced in software. RISC is about putting gates where they count and not wasting them where they don't.
When you view RISC by it's actual principles, and not just by what the letters stand for, it's quite easy to see how SIMD units are entirely compatible. Of course, RISC as a differentiator has been obsolete for decades now and only exists as a point of argument for people who don't understand. RISC was an interesting topic...in 1988. You're 30 years behind.
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You don't understand what "this guy" (David Patterson and Andrew Waterman) is writing. Their main complaint with regular SIMD is that it makes the instruction set grow quickly over time, as CPU performance is scaled up and SIMD units are made wider but old instructions still need to be supported for backward compatibility. They support vector instructions similar to ARM SVE, as those allow scaling up the performance by adding wide execution units without requiring the introduction of new instructions at the
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AVX can get wider too if it makes sense.
No, if you want to make AVX wider, then you would need to introduce a new instruction set. Intel did this several times. They started floating point SIMD with SSE which is 128-bit, then introduced the new AVX instruction set to support 256-bit wide SIMD and then AVX-512 to support 512-bit wide SIMD. If they want to scale up to 1024 or 2048-bit wide SIMD in the future than again, they will have to add new instructions and still need to support the old instructions for legacy software.
With traditional SIMD, y
Hot stuff! (Score:2)
FTA: "30 to 40 megawatts..."
"first, a feeble spark, next a flickering flame, then a mighty blaze, ever increasing in speed and power." - Nikola Tesla
K is faster than what LINPACK indicates (Score:2)
K was listed at number 10 in Nov-2017 benchmark and about 1/9th the speed of the fastest machine. But on HPCG benchmark (http://www.hpcg-benchmark.org ), it was listed number 1. Even now, it is number 2 behind the Summit in HPCG. Not bad for a computer debuted in 2011. Hope they can maintain performance on HPCG as well.
The proposed computer's LINPACK power efficiency is good but not that impressive. Summit is 8.8 MW and proposed computer is 8 times faster at about 4-5 times power consumption. So efficiency
ARM supercomputers (Score:2)
Remember over a decade ago when people were claiming that Apple replacing PowerPC CPUs for Intel CPUs would never ever happen?
We still have people here on Slashdot and on Mac-related forums claiming that Apple will never ever replace Intel CPUs with their own ARM CPUs.
We now have supercomputers built with ARM CPUs. Given Apple's love of computing-power-to-watts ratios, and their need to control as many parts of their hardware as possible, it's only a matter of time. ARM-powered Macs are coming.
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Except that 5 or 10 years ago, Apple didn't have ARM CPUs powerful enough to hold their own against Intel's i3/i5/i7 CPUs. And now they're designing their own, custom-made for their needs. And seeing the low-power, low-end CPU they're using in their MacBooks, Apple could swap to ARM tomorrow and the MacBook computing power would actually increase while lowering the cost.
And ARM comput
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You mean we have ARM based supercomputers planned or being built.... are there any running yet?
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Sure there are! Haven't you seen the new amazing cluster of 16 Raspberry Pi Zero?
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my beolwulf cluster of old cell phones can kick its ass, if I can find all the chargers
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Maybe you're right, but not for the reasons you state:
We now have supercomputers built with ARM CPUs.
Yes, but we also have SPARC powered supercomputers and we haven't had SPARC laptops since Tadpole in the 1990s. What makes for a good supercomputer and a good laptop are quite different things. Part of what makes for a good supercomputer is a fast, very wide floating point unit. But even more, supercomputers live and die on the interconnect. One thing you'll notice is that The Riken, stil very competetive
Looks like a Borg component (Score:2)
That's a terrible chipset, not the good one (Score:2)