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Hardware

The Secret to Tech's Next Big Breakthroughs? Stacking Chips (wsj.com) 116

Posted by msmash from the secret-sauce dept.
Christopher Mims, writing for the Wall Street Journal: A funny thing is happening to the most basic building blocks of nearly all our devices. Microchips, which are usually thin and flat, are being stacked like pancakes (Editor's note: the link could be paywalled). Chip designers -- now playing with depth, not just length and width -- are discovering a variety of unexpected dividends in performance, power consumption and capabilities. Without this technology, the Apple Watch wouldn't be possible. Nor would the most advanced solid-state memory from Samsung, artificial-intelligence systems from Nvidia and Google, or Sony's crazy-fast next-gen camera. Think of this 3-D stacking as urban planning. Without it, you have sprawl -- microchips spread across circuit boards, getting farther and farther apart as more components are needed. But once you start stacking chips, you get a silicon cityscape, with everything in closer proximity.

The advantage is simple physics: When electrons have to travel long distances through copper wires, it takes more power, produces heat and reduces bandwidth. Stacked chips are more efficient, run cooler and communicate across much shorter interconnections at lightning speed, says Greg Yeric, director of future silicon technology for ARM Research, part of microchip design firm ARM.
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The Secret to Tech's Next Big Breakthroughs? Stacking Chips More

The Secret to Tech's Next Big Breakthroughs? Stacking Chips

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  • Not really a new idea (Score:5, Informative)

    by Rick Schumann ( 4662797 ) on Monday November 20, 2017 @12:24PM (#55588041) Journal
    This was thought of a long time ago and experimented with, but the real problem with it was heat. You stack silicon on top of silicon, and there's heat build-up, and heat kills. The real 'breakthrough' and 'innovation' is being down to the 10nm scale, and other lower-power options, enabling silicon to run cooler yet at faster speeds.

    • Re:Not really a new idea (Score:5, Informative)

      by NicknameUnavailable ( 4134147 ) on Monday November 20, 2017 @12:38PM (#55588209)

      This was thought of a long time ago and experimented with, but the real problem with it was heat.

      No, it wasn't. You can run them at lower power and therefore generate less heat. The issue is that lithographic techniques don't let you get more than a few layers thick before the negative f-theta lenses employed are out of focus. You end up needing nano-positioning stages along the Z-axis, which as a matter of necessity means you need nano-positioning stages along at least 3 corners of a wafer, and along the X/Y (separate from the galvanometers or nanoactuated mirrors behind the negative f-theta lens) in order to keep the wafer aligned in the plane projected by the negative f-theta lens (just forget about doing this stuff with masks without using similarly complex alignment methods on both the wafer and the mask holder.)

      The real 'breakthrough' and 'innovation' is being down to the 10nm scale, and other lower-power options, enabling silicon to run cooler yet at faster speeds.

      No, it isn't. Scaling down allows you to run at lower power for higher frequencies, but you could just as easily reduce the frequency of the chip to spend less power. You end up getting less out of it, but not in terms of FLOPS/Watt - it's just that we focus on the FLOPS aspect more than the Wattage. Scaling along the Z axis has been the issue for a long time, you just can't do it with things in the nanometer range without absurdly complex chip fabrication equipment and effectively building 1 chip at a time (with a lithographic mask you can make hundreds or thousands of ICs at the same time because the Z axis changes relatively little across the X and Y axis, but when you're talking about building a little tower suddenly you have to deal with a host of changes.) To use the building analogy: you can tilt a 1-story building 5, even 15 degrees, and still drop a rock above a room to land on the roof of that room without knowing anything beyond the X and Y coordinate of the room relative to the floorplan - if you try the same thing on the 40th floor of a skyscraper tilted at even 1 degree you aren't going to be anywhere near it, you'll just hit an exterior wall several stories down.

      • Re:Not really a new idea (Score:5, Informative)

        by religionofpeas ( 4511805 ) on Monday November 20, 2017 @12:46PM (#55588287)

        The issue is that lithographic techniques don't let you get more than a few layers thick before the negative f-theta lenses employed are out of focus

        They aren't making 3D chips. They are making regular chips, and then stack the dies directly on top of each other.

        • You seem to have misread the comment. The issue in the past has been the actual process of making them in 3D (as opposed to heat, as the person I responded to had suggested.) I never said you couldn't stack a bunch of 2D chips manufactured separately (or in parallel, "separately" meaning "not a monolithic tower.")

          • Look this entire conversation has nothing to do with lithography, and the process of making a chip stackable has always existed, they just haven't done that. No one here is talking about 3D silicon other than you.

            As for your comment about heat, that was stupid as well. Yeah scale back heat by lowering the frequency, as if what designers were really after was something that runs slower. You just traded off the one thing no one wanted to trade off and declared the problem solved. Bravo.

      • From what I understand, there is a drawback when trying to use the smallest lithography and 3D in that 3D transistors like FinFET have been necessary for a while to combat leakage. [wikipedia.org]
      • The Cray-3 was using 3D chip stacking back in the early 1990's, but it was with low-integration gallium arsenide chips. Even so, the cooling was insane - immersion in a flourocarbon fluid. https://en.wikipedia.org/wiki/... [wikipedia.org]

    • Yeah, just what I was thinking- Secret from 1995 maybe. I remember "upgrading" 8 bit computers this way, of course, not internal to the package.

      If you somehow could come up with good cooling in the package itself though, it would work.

      • I (a software guy) brought up this idea in the late 70s to a friend in hardware (I think he was at HP at the time). He figured the problem would be heat dissipation. He wasn't a chip designer though.

    • this was how the processors in the X-MP were made... two chips stacked. ran into a former Chippewa Falls worker, 2000-ish, who had a dud he's kept in a matchbox. I touched it. and it didn't file any charges....

      • Re: (Score:1)

        by Anonymous Coward

        Cray T90 ... the original package on package memory system? (More than 20 years ago.)

        http://img.hexus.net/v2/features/armarivisit/images/t90_system_board_big.jpg

        The memory module uses stacks of 20 IC packages * two stacks per array * 16 arrays = 640 physical memory ICs per module. They solved the heat problem with Fluorinert liquid immersion cooling ;-)

    • Re:Not really a new idea (Score:5, Interesting)

      by pz ( 113803 ) on Monday November 20, 2017 @01:43PM (#55588773) Journal

      Indeed. I spent part of my doctoral work trying to understand the heat issues and trying to come up with solutions. Fundamentally, heat extraction is a surface-area process, whereas heat generation is a bulk process. Thus as you start to increase the thickness of the material, the heat, in general, goes up with the volume, or r^3, but the cooling capacity goes up with the surface, or r^2. If you start from an approximately planar structure, for a while, this is OK, but very quickly you run into trouble. The situation does not scale indefinitely without uncontrolled temperature rise.

      One way of mitigating the issue when you are using a cooling fluid is to make the 3D structure porous, and flow the fluid through the device. We did just that. If relying on convection, you can fill the chip carrier with cooling fluid, and make a series of towers instead. We found the thermal latency was too slow for most applications in that case, but there were lots of assumptions that might have been incorrect for a specific situation.

      If you are willing to flow coolant, then the obvious way to make it scale is to create a branched structure, not unlike blood vessels, where there is a central macroscopic pump that circulates the coolant through a network of finer and finer tubes until the heat has been extracted, and then through the inverse network of thicker and thicker tubes until you get back to the pump (and external cooling mechanism). Nature has this sort of arrangement all over the place.

      My conclusion was that fundamentally 3D structures were going to have limited applicability without active cooling unless someone discovered the equivalent of room-temperature superconductivity for phonons (and thus heat) in an electrical semiconductor.

    • This was thought of a long time ago

      In 1991, to be exact [wordpress.com].

    • I remember seeing about 40 years ago either in Radio Electronics or Popular Electronics instructions to make an ultra-compact multi-meter, where the DIP chips were staked together, and wires and components run on the sides of the chips stack...

      • There's been loads of chip stacking in the past. The commonest example from back in the day is stacking DRAM chips, and the commonest example from today that people are actually familiar with is probably the Raspberry Pi. Its SoC has a DRAM chip slapped on top of it.

  • Benefits and drawbacks (Score:3)

    by Baron_Yam ( 643147 ) on Monday November 20, 2017 @12:28PM (#55588095)

    Benefits: 3D circuits (with the extra potential complexity that implies), smaller chip for the same complexity (with reduced signal distance and heat generation)

    Drawback: Getting heat out of the chip as only the outer layers will be next to a heat sink. Then again, we're talking 3D here... maybe they'll figure out how to weave a mesh of tiny heat pipes around the circuits.

    • ...with the extra potential complexity that implies...

      High density routing on circuit boards is also complex.

    • Personally the big one I'm looking forward to is single-element chips, not necessarily because they will be of great use, but just because they'd be freaking cool. Aluminum for instance has p-type, n-type, insulating, and conductive crystal morphologies, all of which can be generated by the different cooling rates from a molten phase along with the peak temp while molten. Using something akin to an SLS 3D printer you could conceivably print a complete CPU out of solid Aluminum (theoretically, tuning the p

    • Re: (Score:2)

      by Agripa ( 139780 )

      Then again, we're talking 3D here... maybe they'll figure out how to weave a mesh of tiny heat pipes around the circuits.

      Heat pipes are not as useful in this case as one might think. Heat pipes already require heat spreaders because they can only support up to a limited power/area before nucleated and then film boiling prevents the heat pipe from operating. We passed that power/area point with *one* layer of silicon several generations ago.

  • Urban Crime (Score:5, Funny)

    by sycodon ( 149926 ) on Monday November 20, 2017 @12:28PM (#55588101)

    How long until little bits of data on their Lightcycles start causing trouble?

  • Heat (Score:1)

    by Ayano ( 4882157 )
    It's more the advances in heat mitigation, this I wager will be the new bottleneck rather that chipset size.
  • Original BeagleBoard stacked the ARM MCU, the RAM, and the NAND flash in package on package (PoP):

    https://beagleboard.org/beagleboard

  • Many issues (Score:2, Insightful)

    by Anonymous Coward

    In my EE grad class in 1998, we discussed chip stacking. Given the 2D manufacturing tech at the time (where chips are designed and manufactured in 2D then cut and seated in a larger housing), the biggest issue was literally how to bridge the 3rd dimension. Any imperfection in the wafer would mean an uneven seat when stacked. You have heat dissipation issues, which means a limitation in clock speed. And the simple act of aligning the layers at nm distances wasn't possible at the time. To get around this

    • Re: (Score:1)

      by Tx ( 96709 )

      It would revolutionize the industry, but there are a ton of technical issues to overcome.

      Well, since it appears to be being done right now, presumably technology has moved on since your EE grad class in 1988?

      • It would revolutionize the industry, but there are a ton of technical issues to overcome.

        Well, since it appears to be being done right now, presumably technology has moved on since your EE grad class in 1988?

        Since he never said anything to the contrary, presumably you were more interested in trying to sound superior rather than learning about the past challenges from those who lived them.

    • Re:Many issues (Score:4, Interesting)

      by religionofpeas ( 4511805 ) on Monday November 20, 2017 @01:17PM (#55588557)

      Here's an image:
      http://electronicpackaging.asm... [asme.org]

      As you can see, there's no need for nanometer alignment. Small imperfections aren't a problem either.

    • Even the humble MicroSDXC card uses 16 stacked dies. And have done since 2014

      https://arstechnica.com/gadget... [arstechnica.com]

      To boost capacity, SanDisk said in a statement that it had "developed an innovative proprietary technique that allows for 16 memory die to be vertically stacked," and each memory die is "shaved to be thinner than a strand of hair." The new card will be available exclusively through Amazon.com and BestBuy.com initially, and as a Class 10 SD card it offers minimum read and write speeds of 10 megabytes per second. This should be sufficient for recording 1080p video, according to the SD Association's speed ratings.

  • If they solved the problem of the middle slice of the pancake having more heat than it should, 3D chip are a good solution. Plus it is easier by order of magnitude to do flat chip. So price factors in.

    • There are plenty of applications where the chips are already very low power, so stacking doesn't cause heat problems.

  • looks familiar (Score:3)

    by Ubi_NL ( 313657 ) <joris.benschop@g ... ail.com minus pi> on Monday November 20, 2017 @12:37PM (#55588193) Journal

    Isn't that the magical breakthrough that made cyberdyne so much money?
    https://i.ytimg.com/vi/DGQlYCFT7d0/maxresdefault.jpg [ytimg.com]

  • Memory crystals, full 3-D storage. The Future. You heard it here first.

  • Electrons don't travel longer distances (Score:1)

    by Anonymous Coward

    Your physics teacher once explained this to you by pointing out that water molecules don't need to travel from the faucet all the way through the hose for water to come out when you open the faucet. The molecules that enter the hose push the molecules that are already in there out the other end almost instantly. The drift velocity of electrons is on the order of millimeters per hour. The signal however travels as a wave at roughly 200000 kilometers per second, two thirds of the speed of light in vacuum.

  • Seriously, R&D on this has been ongoing since at LEAST the 80s and more likely the 70s.
    One of the bigger issues is that surface area to volume really drops, so will likely have multiple heat sinks with microtubes built in between chips to carry off heat.

    • One of the bigger issues is that surface area to volume really drops

      You can make plenty of useful applications by stacking 2 or 3 layers, for instance stacking RAM and Flash on top of a CPU to take advantage of wide buses, and different technologies. Think smart phones and low power gadgets, not stacking a dozen i7 CPUs on top of each other.

      • yeah, I have thought that a nice IO chip would be perfect for this. USB and Ethernet do not generate lots of heat, though that would be 1G and under.
        In fact, if done up right, a small chip with CPU/ram could serve as buffering with wifi, USB, Ethernet, SATA, SCSI, etc.

  • Mirror to avoid paywall (Score:3, Informative)

    by Hal_Porter ( 817932 ) on Monday November 20, 2017 @01:37PM (#55588717)

    https://archive.fo/Af3EZ [archive.fo]

    By Christopher Mims
    Nov. 19, 2017 9:00 a.m. ET

    A funny thing is happening to the most basic building blocks of nearly all our devices. Microchips, which are usually thin and flat, are being stacked like pancakes.

    Chip designers-now playing with depth, not just length and width-are discovering a variety of unexpected dividends in performance, power consumption and capabilities.

    Without this technology, the Apple Watch wouldn't be possible. Nor would the most advanced solid-state memory from Samsung, artificial-intelligence systems from Nvidia and Google, or Sony's crazy-fast next-gen camera.

    Think of this 3-D stacking as urban planning. Without it, you have sprawl-microchips spread across circuit boards, getting farther and farther apart as more components are needed. But once you start stacking chips, you get a silicon cityscape, with everything in closer proximity.

    The advantage is simple physics: When electrons have to travel long distances through copper wires, it takes more power, produces heat and reduces bandwidth. Stacked chips are more efficient, run cooler and communicate across much shorter interconnections at lightning speed, says Greg Yeric, director of future silicon technology for ARM Research, part of microchip design firm ARM.

    While the principles that underlie 3-D microchips are straightforward, making them is anything but. First proposed in the 1960s, the technology has sporadically appeared in high-end applications, such as military hardware, Mr. Yeric says.

    But stacked-chip offerings from most major chipmakers-AMD, Intel, Apple, Samsung and Nvidia-plus smaller, specialized companies like Xilinx, have been around only five years or so, says Sinjin Dixon-Warren, an analyst at microchip research firm TechInsights. What changed? Engineers started running out of other ways to squeeze more performance out of microchips.

    Stacked chips are frequently part of a "package" of other scrunched-together chips. In addition to saving space, this lets makers create many different chips-with different manufacturing processes-and then more or less literally glue them all together. The "3-D system in package" approach contrasts with the "system on a chip" approach frequently used in mobile phones, where all the different components of the phone are etched on a single piece of silicon.

    One of the most advanced 3-D chip packages has powered the Apple Watch since its introduction, Mr. Dixon-Warren says. Thirty different chips are hermetically sealed inside a plastic envelope. To save space, memory is stacked on top of the logic circuit, he says. The watch couldn't be so compact without chip stacking.

    But where Apple's chips are stacked only two stories high, Samsung has produced a veritable silicon high-rise. Samsung's V-NAND flash memory, used for storing data in phones, cameras and laptops, has 64 chips placed one atop the other. Samsung just announced that a future version will have 96 layers.

    Nvidia's Volta microprocessors are built for artificial intelligence, with up to eight layers of high-bandwidth memory stacked onto the GPU. Shown, Nvidia chips exhibited at the Computex show in Taipei in May.

    Memory is a natural application for chip-stacking technology, since it solves a problem that has long plagued chip designers: Adding more cores to anything from an iPad to a supercomputer didn't translate to hoped-for speed gains because of the communications lag between logic circuits and the memory they need to do their jobs. Sticking memory right on top of chips allows for many more short connections between the two.

    That's how Nvidia's built-for-AI Volta microprocessors work, says Brian Kelleher, the company's senior vice president of hardware engineering. By stacking up to eight layers of high-bandwidth memory directly on top of the GPU, these chips are breaking records in processing efficiency.

    "We are power-limited," says Mr. Kelleher, referring to the amount of

  • People have been doing that [infinetivity.com] for a while now.

    • If you subscribed to the WSJ you'd realise that the result is absolutely nothing like that garbage you just posted.

      • If you'd think about it for more than one millisecond before replying, you'd see that I was kidding.

        • Actually all I see is an ignorant statement. There are no queues outside of your language because this is a written forum, nor any indication inside the language that would tip the scales between a balance of facetious and ignorant. This being Slashdot I'm now defaulting to the latter.

          I know emoticons aren't trendy on Slashdot, but send us a smiley if you won't want to be misunderstood next time :-)

  • One simple step that could happen today is making some additional clearance under a BGA to allow capacitors to be placed under part of the package close to the power pins that seem more often than not to be centrally clustered. Or maybe, add capacitors to the underside of the package interleaved between the appropriate pins so the whole assembly can be installed in one go and not need capacitors on the flipside of the board.

    • How about components embedded inside the PCB ?

      https://www.electronicproducts... [electronicproducts.com]

      • so the copper core solder balls act as a stand-off... that is pretty cool. I wonder what production difficulties that introduces. I can imagine the bga packages just rolling around all over the place when the solder is flowed or the board suffering from thermal stresses over its life. I wonder if a standard BGA can be re-balled with them easily.
  • to Skynet and Judgement Day.

  • Seriously, they always knew that this would be far more practical in terms of power and efficiency for silicon based circuits than putting everything on a flat die. The reason they didn't do so wasn't because they didn't know it would be any better, it was because it wasn't really feasible from a cost-gain perspective.

    I asked my shop teacher in school during an section on electronics about this back in the 1980's, and he told me back then that the only reason they didn't already make 3d integrated circu

  • wasnt it one of the 386 486 586 sx dx whatever chips that you would upgrade by literally jamming another chip on top? i was little but to this day rememeber my dad lolling about it.

    • >wasnt it one of the 386 486 586 sx dx whatever chips that you would upgrade by literally jamming another chip on top?

      If I recall correctly, the 386sx was internally 32 bit but had an external 16bit bus, while the 486sx had a disabled or missing FPU. The dx variants were the ones that didn't have those limitations.

      So far as I know, neither was upgradable by sticking another chip on top... though some motherboards would allow the CPU to be completely replaced.

  • That's a stacker. I believe earlier stuff like the BeagleBoard was as well.

  • https://www.investorvillage.com/smbd.asp?mb=2287&mn=125&pt=msg&mid=17719312

  • I realize the WSJ hires people. And people post articles on /. to be read by even more people.

    But the /. people have known about chip stacking for decades. Granted it has been very difficult to do previously. But so were nanometer chips back when nobody had a process that was less than a micron. No doubt WSJ will want to let their readers know the micron barrier was finally breached.

    WSJ and timely, accurate articles about the electronics, fab processing, computer industries are fantasies. They have neve

  • Take eight 64k x 1 memory chips, stack them, solder all pins together except for the data pin, then run a wire from each data pin, and you've just made a 64k x 8 memory module. Nothing new about this.

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