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Scientists Turn Memory Chips Into Processors To Speed Up Computing Tasks (sciencedaily.com) 73

An anonymous reader quotes a report from Science Daily: A team of international scientists have found a way to make memory chips perform computing tasks, which is traditionally done by computer processors like those made by Intel and Qualcomm. This means data could now be processed in the same spot where it is stored, leading to much faster and thinner mobile devices and computers. This new computing circuit was developed by Nanyang Technological University, Singapore (NTU Singapore) in collaboration with Germany's RWTH Aachen University and Forschungszentrum Juelich, one of the largest interdisciplinary research centers in Europe. It is built using state-of-the-art memory chips known as Redox-based resistive switching random access memory (ReRAM). Developed by global chipmakers such as SanDisk and Panasonic, this type of chip is one of the fastest memory modules that will soon be available commercially. However, instead of storing information, NTU Assistant Professor Anupam Chattopadhyay in collaboration with Professor Rainer Waser from RWTH Aachen University and Dr Vikas Rana from Forschungszentrum Juelich showed how ReRAM can also be used to process data. This discovery was published recently in Scientific Reports. By making the memory chip perform computing tasks, space can be saved by eliminating the processor, leading to thinner, smaller and lighter electronics. The discovery could also lead to new design possibilities for consumer electronics and wearable technology.
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Scientists Turn Memory Chips Into Processors To Speed Up Computing Tasks

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  • by thygate ( 1590197 ) on Wednesday January 04, 2017 @05:05AM (#53603103)
    like using truth tables in ROM as logic devices ?
    • Re:truth tables (Score:5, Interesting)

      by Anonymous Coward on Wednesday January 04, 2017 @05:22AM (#53603145)

      More closely to FPGA from my understanding since it is special ICs that use "Ternary number system" (IE: 0,1,2 instead of binary 0,1) Which actually would allow a LOT of different types of 'in-place' calculations to take place on data via FPGA subsets of the memory IC.

      The problem with this is.... We already have the technology to allow in-place memory access via FPGA subsets... it just isn't very secure (would require a lot of kernel level access to manage who can write to the FPGA section) etc. and honestly doesn't have a lot of -practical- applications.

      This is a great proof of concept, but don't expect any device to have this within 7~10 years easily. This research is impressive, but I don't see it being useful until additional research/algorithms/(god I hope security)/programs are designed to make use of it in specialized hardware Then (MAYBE) into consumer grade equipment.

      • Interesting to compare this to Micron's Automata processor, which is using standard DRAM for computations, taking advantage of massive parallelism for specialized tasks involving unstructured data. But this application is for a specialized RAM which probably has less general use. https://www.micronautomata.com... [micronautomata.com]

      • Meanwhile, Kaby-Lake is consuming Intel's silicon density gains with 4K DRM decoding... it's an essential feature that consumers will miss if it's not implemented in hardware, it's all kinds of IP protected, and it's god-awful expensive in terms of real-estate, just what the world needs, eh?

        • by cfalcon ( 779563 )

          I don't think they "consumed their gains" with it. Kabylake is on the same process, and is almost the same chip, as Skylake. It's an odd feature to get such billing, and it doesn't have to be DMCA protected for Kabylake to play it- it just supports that DRM in hardware. That's not very great, IMO, but I can see why people will like the idea. But anyway, supporting H.265 on chip seems like the sort of thing Intel would do to have a marketable feature, the DRM support is just what makes Netflix happy.

        • I thought the whole thing with 4k was that Netflix only supports playready 3 on PCs, which Microsoft only implements in edge, while edge can't decode HEVC without hardware support in the CPU, and kaby lake is the only CPU that does so.

          It's a really stupid set of dependencies.

    • No, more like integrating RAM and processor on a single die...

      • by Gorobei ( 127755 )

        Exactly, but the article seems to be adding confusion by talking about low-level physical implementation. It's a good rule of thumb that claiming a low-level idea will somehow punch through four or five layers of abstraction to get a high-level paradigm shift is usually wrong (maybe quantum computing will prove the exception,) but usually the high level ideas remain the same and just get better as the underlying mechanics improve. We've got a lot of experience with transputers, connection machines, GPUs, pa

    • by skids ( 119237 )

      From glossing through the article what they are doing is leveraging memristors... a high level way to look at it is they can write two values in sequence to a memristor without clearing it in between writes and it adds them because the values accumulate in the analog state. But there's some scheme to deal with carrying between memristors layered on top, and they also leverage the ability to write one word to the low side of the gate simultaneous to writing the other to the high side Not an entirely new i

  • Is this a discovery or an invention? Is it a case of making ReRAM do something it wasn't designed or expected to do, or has someone built a new thing that connects to/updates ReRAM?

  • by Gravis Zero ( 934156 ) on Wednesday January 04, 2017 @07:07AM (#53603303)

    Unless I'm missing something, this won't result in "faster computing" but rather having more bandwidth for RAM.

    Currently, all computer processors in the market are using the binary system, which is composed of two states – either 0 or 1. For example, the letter A will be processed and stored as 01000001, an 8-bit character.

    However, the prototype ReRAM circuit built by Asst Prof Chattopadhyay and his collaborators processes data in four states instead of two. For example, it can store and process data as 0, 1, 2, or 3, known as Ternary number system.

    Because ReRAM uses different electrical resistance to store information, it could be possible to store the data in an even higher number of states, hence speeding up computing tasks beyond current limitations.

    If they wanted, they could already encode more data per bus line and put a translator by the RAM. However, literally none of this is talking about doing any computing using memory. It kinda seems like maybe a non-technical person wrote this press release.

    • For example, it can store and process data as 0, 1, 2, or 3, known as Ternary number system.

      The Ternary, or Base-3, number system uses digits 0, 1, and 2 or (for Balanced Ternary) -1, 0, and +1. The Base-4 system with digits 0, 1, 2, and 3 is properly referred to as the Quaternary number system.

  • The 3 state RAM doesn't actually do computation.... if you want that... take a look at an old idea of mine...http://bitgrid.blogspot.com/

  • by gavron ( 1300111 ) on Wednesday January 04, 2017 @07:42AM (#53603361)

    A memory chip is not a processor.
    The *summary of* the article didn't say what the article did.
    Nothing the summary says is close to what is true.

    NO MEMORY UNIT WILL PERFORM CPU FUNCTIONS at less than 2 orders of magnitude worse (that's 1/100 performance/power) today.

    There's no "discovery" here. You can use stones and sticks to compute. Using a memory chip is far more advanced. And just as stupid.

    Slow day on slashdot?

    Yes. I signed this post. Because I'm in the industry. I'm not a troll. I get to call out when people put out stupid articles where they summarize stupid research papers that have nothing to do with reality land. Like this one.

    E

    • It's a quite fascinating piece of work [nih.gov] and baffling for someone like myself with a CS degree but no real understanding of semiconductors, so it's no surprise the journos couldn't really report well on it. A brief glance at the paper shows the researchers make no claims about this ever being a mainstream technology. I think they're doing the usual academic thing of just learning about possibilities for possibilities' sake. It seems to indicate fundamental properties in memoristor devices, but it's not "calcu
    • by suutar ( 1860506 )

      obxkcd: http://xkcd.com/505/ [xkcd.com]

    • A memory chip is not a processor.
      The *summary of* the article didn't say what the article did.
      Nothing the summary says is close to what is true.

      NO MEMORY UNIT WILL PERFORM CPU FUNCTIONS at less than 2 orders of magnitude worse (that's 1/100 performance/power) today.

      There's no "discovery" here.

      You're right. It was an ACHIEVEMENT, not a DISCOVERY.

      Isn't this a 4-state memristor? Memristors can do computing, just as OR, NOR, and NOT gate circuits hard-wired can do computing. I am in the industry, but on the materials not device side, so feel free to correct me.

      BTW, memristors were postulated in the 1950's. It completes the group of computing elements: resistor, capacitor, inductor, and then memristor. The last had not been demonstrated until a very few years ago.

      • by gavron ( 1300111 )

        It's not a memristor. See this article [cnn.com] which does a much better job of explaining it than WikiPedia [wikipedia.org].

        Memristors by definition is not a stateful electronic component, so, to answer your question, no, it's not a 4-state memristor. The original article does talk about "states" but it refers to the ternary numerbing system available in the device. Ternary is better than binary for efficient storage (log base 3 of n vs log base 2 of n) but hopelessly inefficient for actually accessing it or doing anything wit

  • by GuB-42 ( 2483988 ) on Wednesday January 04, 2017 @08:11AM (#53603421)

    Both the summary and the article don't know what they are talking about. Reading these will only confuse you.
    Read the paper here instead : http://www.nature.com/articles... [nature.com]

    To summarize :
    - ReRAM is a promising type of non-volatile memory.
    - Earlier, it was discovered that ReRAM cells could be used to perform computations. This is not news.
    - Multi-level ReRAM, which is able to store more than 2 states per cell exist. This is similar to MLC/TLC for flash memory. This is not news.
    - The new thing is that with using 6-state cells, they managed to do calculations in base 3 directly. More generally, they said it would be possible to do base-n using 2n-state cells. This is good because higher bases means less cells are required for the same computation.

    • by slew ( 2918 )

      Although this modular arithmetic (e.g., base-3) angle they are working at might be theoretically interesting, there probably aren't enough killer applications to make it worthwhile to make a special ram that runs modular arithmetic configurations. Just like historical so-called Graphics ram (which didn't really do graphics, but optimized bit-planes clears/masks, simple blends and window operations) eventually didn't survive the march of DRAM economics which greatly favors standard products over niche produ

    • THIS is why i read slashdot. Sure, article summary's are sometimes atrocious just like they are on every other site (and on other sites often worse) but I always know I can read the comments on slashdot to get the most informed reviews (and sometimes brand new information) from people in the actual Tech world who know what they are talking about. Thanks GuB-42!
    • by Doke ( 23992 )

      Specifically, they managed to do addition, with modulus, and without any overflow detection, in multi-state ReRAM. Basicly, each cell can hold an analog level, that can be read as 0 through 5. You write it by resetting it to 0, then hitting it with the right constant current for the right amount of time to set it to a particular value, for example 3. If you skip the reset part, and write a 2, the effects add, and the cell ends up with a 5. If you write too much, it wraps around. Theoretically, you c

  • by Anonymous Coward

    The concept of "Processor-in-Memory" (PIM) has been extensively researched in the high-performance computing community to avoid moving data to a distant processor for certain operations. Nothing came of it.

    Over the decades, architectures have been introduced that included operations like increment and decrement in memory. These atomic operations were useful in building parallel computing constructs.

  • Resistive switching memory *is* memristance. https://en.wikipedia.org/wiki/... [wikipedia.org] Leon Chua has been researching memristors for about half a century, and R. Stanley Williams has many article and lectures about how memristors can be used in place of NAND gates in CPUs (i.e. to perform computing tasks) as well as memory. I encourage everyone to use the right terminology when discussing and introducing memristors to a new audience, especially since they are being rediscovered at an increasing rate recently. R.
  • DRAM process has additional requirements in order to reliably create storage capacitors in the small size the process node can sustain. Microprocessors are best manufactured in logic-optimized processes. You usually sacrifice area if you implement logic on DRAM, and you risk much more if you try to implement DRAM on logic-optimized process.
    If you produce a lot of junk because you tried to do something that a process flow is not reliably able to do, then your costs skyrocket and you may have been better off

  • Certainly a DRAM-derivative chip will have literal assloads of space for LUTs. But it'll lack the other magic-sauce component of those other reprogrammable logic devices, FPGAs and CPLDs: routing. The result is typically a non-pipelined quasi-CPU with as big a machine state as there's dedicated RAM for it (somewhere around 40 bits at most, these days), on top of which a proper CPU gets written (using some other ginormous chunk of RAM).

    And this ain't new, or difficult, or novel in any way.

    What I wonder is ho

  • by gweihir ( 88907 ) on Wednesday January 04, 2017 @02:18PM (#53605739)

    There are reasons CPU and RAM are separated. These are good reasons. The whole article is unmitigated nonsense, except for a very small set of special-purpose computations that can already be done with FPGAs anyways.

  • Cray, of course:

    https://en.wikipedia.org/wiki/Cray-3/SSS

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