big.LITTLE: ARM's Strategy For Efficient Computing 73
MojoKid writes "big.LITTLE is ARM's solution to a particularly nasty problem: smaller and smaller process nodes no longer deliver the kind of overall power consumption improvements they did years ago. Before 90nm technology, semiconductor firms could count on new chips being smaller, faster, and drawing less power at a given frequency. Eventually, that stopped being true. Tighter process geometries still pack more transistors per square millimeter, but the improvements to power consumption and maximum frequency have been falling with each smaller node. Rising defect densities have created a situation where — for the first time ever — 20nm wafers won't be cheaper than the 28nm processors they're supposed to replace. This is a critical problem for the mobile market, where low power consumption is absolutely vital. big.LITTLE is ARM's answer to this problem. The strategy requires manufacturers to implement two sets of cores — the Cortex-A7 and Cortex-A15 are the current match-up. The idea is for the little cores to handle the bulk of the device's work, with the big cores used for occasional heavy lifting. ARM's argument is that this approach is superior to dynamic voltage and frequency scaling (DVFS) because it's impossible for a single CPU architecture to retain a linear performance/power curve across its entire frequency range. This is the same argument Nvidia made when it built the Companion Core in Tegra 3."
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Powered-down circuits have no leakage. Also a "little" implementation has vastly lower leakage than a bigger core.
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Royalties in many licenses allow an unlimited number of CPUs on the same chip. You pay the royalty per design per chip.
Power not die area efficient. (Score:1)
This solution _might_ be more power efficient. But it can not be more die and space efficient. Looking at keeping die sizes down to place more other crap on the die's, a ginormous core complex does not really fit the bill. Besides, if you want to keep core context switch times low, you must keep all caches etc on the larger cores hot and that draws power. This solution probably fits when you start a game, so that you have an explicit trigger to switch to the larger cores. If you are talking on demand ultra
Re:Power not die area efficient. (Score:5, Insightful)
This solution _might_ be more power efficient. But it can not be more die and space efficient
Two words: Dark Silicon. As process technologies have improved, the amount of the chip that you can have powered at any given time has decreased. This is why we've seen a recent rise in instruction set extensions that improve the performance of a relatively small set of algorithms. If you add something that needs to be powered all of the time, all you do is push closer to the thermal limit where you need to reduce clock speed. If you add something that is only powered infrequently, then you can get a big performance win when it is used but pay a price when it isn't.
TL;DR version: transistors are cheap. Powered transistors are expensive.
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Agreed.
If there is ever the perfect fits all solution (such as Intel tries to build) it won't be for a very long time. If ever.
Transistors are cheap, just built for what your target usage is.
I seem to remember something about AMD and some sort of interconnect tech that (one day) allows you to quickly/cheaply/easily interconnect modular chip bits and really easily build for a target market.
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At 28nm? It's the difference between 'tiny' and 'almost as tiny.' The packaging is many times the size of the chip, so if you can get both chips in one package it won't add anything. Power is more important.
Re:Power not die area efficient. (Score:4, Informative)
Found it:
http://semiaccurate.com/2013/05/01/sonics-licenses-fabric-tech-to-arm/ [semiaccurate.com]
"Sonics and ARM just made an agreement to use Sonics interconnects patents and some power management tech in ARM products."
"If Sonics is to be taken at face value on their functionality, then you can slap just about any IP block you have on an ARM core now with a fair bit of ease."
This is kind of relevant too, the internet will eat all our electricities:
http://www.theregister.co.uk/2012/11/26/interview_rod_tucker/ [theregister.co.uk]
"and if we don’t do anything, it could become ten percent between 2020 and 2025"
Although if you read it, the lion shares of internet electric usage is actually those amp happy DSL connections we have.
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Whoops, replied to the wrong message...
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An asymmetric SMP machine is nothing new.
That's a tautology. An asymmetric symmetric multiprocessor can't exist by definition, therefore it can't exist as a new thing by definition.
old news (Score:3, Informative)
Advertising much?
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CPU caches are designed to minimize latency.
These two goals are at odds with each other.
It is no surprise that there is a market for GPU's. I think the surprise was that 3dfx could offer much-better-than-using-the-cpu performance so cheaply.
big.LITTLE (Score:2)
Some marketdroid had a field day finding that name, sheesh...
I would have added "i" in front of it, personally. Everybody knows i-anything is teh kewl these days.
Re:big.LITTLE (Score:5, Funny)
Are you proposing the name IBig.ULittle?
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How about LITTLE.big:ARM-venture.
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Code name the next ARM architecture "horn". Then you can have little.BIG.horn (ducks to avoid arrows).
with apologies to the Pythons (Score:2)
Car analogy (Score:2)
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Is that so? ;)
Mercedes Benz E300 BlueTEC Hybrid 65 mpg 111 g/km (201bhp 2.1l)
Peugeot 3008 Hybrid4 74 mpg 99g/km (200bhp 2.0l)
The Prius is old news.
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So basically a KERS type system? e.g. a small ICE for range and a much more powerful electric/flywheel motor for acceleration? Depending on usage that may make more sense than the current system. An ICE that can sustain say 90mph whilst still providing some left over energy to be stored for acceleration. Worst case is you do lots of high speed starts and stops (e.g. driving like a tool in traffic or urban areas) which leaves you with only the ICE power - which would likely still be enough for most purpo
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I've wondered why they haven't done that yet.
Both the cars I've mentioned have something similar.
No expensive complex linkage in the 3008 (diesel front, electric rear)
No expensive batteries or big electric in the Merc (electric just there to maintain 70mph)
There is one boutique sports car with an engine that is just a generator.
So give it another 10 years.
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The merc's like that, except backwards.
Diesel to get up to speed and electric to keep you there, charging from the diesel when the small battery is flat.
Clever sticks those Germans.
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I'm not sure but I think they're summing the power of the dino engine and the electric engine.
I have the same engine in my Ford and it puts out 138bhp (It's an engine by PSA)
However the diesel powers the front wheels and the electric the rear.
This allows you to use both at the same time and forgo the heavy, complex and expensive linkage in normal hybrids.
Thing is, if it only produces 99 g/km.
Now, the Merc is quite different, the electric engine is small, as is the battery and it's packed somewhere in the tr
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However the diesel powers the front wheels and the electric the rear.
Which means the diesel is still mechanically connected to the road. Either you have an incrementally variable transmission, and chances are the diesel is not going to be running anywhere near its optimal conditions, or you have a continuously variable transmission, in which case you've got tons of losses anyway. The whole point of an electric transmission is to allow the engine to operate in the narrow band it wants to, and use the electric motor to provide the wide, efficient operating range you need.
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There's one car like that, some boutique sports car.
Of course, there's no reason why you can't just have the car disengage the clutch and charge the battery that's in the boot.
For reference the transmission is an "electrically controlled manual".
Assuming this means 6 speeds and clutch but electronic auto/semi controlls.
So, use the diesel to accelerate up to 88 miles and hour.
Then disengage the clutch, shutdown the diesel and maintain with the electrics.
When you're out of leccy, start up the diesel and charg
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For reference the transmission is an "electrically controlled manual".
When I say an "electric transmission", I'm referring to a diesel-electric drive, where a diesel engine powers a generator which powers one or more motors. The electrical wiring replaces the traditional mechanical linkages in the transmission.
Re: Car analogy (Score:2)
Yes I realised, the statement about the gear box was unrelated.
The reason I mentioned the gearbox was because with it it's possible to electrically disengage the clutch, there's no clutch pedal. Meaning with appropriate firmware it can run as a diesel electric drive system. I think I'll ask them.
Anyway, I've found my next car! 8D
They come into my price range next year.
It's not necessarily ARM's solution (Score:5, Insightful)
Big/little is a lazy way out of the power problem... Because instead of investing in design and development and in fine grained power control in your processor, you make the design decision of, "Heck with this -- silicon is cheap!" and throw away a good chunk of silicon when the processor goes into a different power mode... You have no graceful scaling -- just a brute force throttle and a clunky interface for the Kernel.
So, not all ARM licensees have been convinced or seen the need to go to a big/little architecture because big/little has that big disadvantages of added complexity and wasted realestate (and cost) on the die. Unlike nVidea (Tegra) and Samsung (Exynos), Qualcomm has been able to thus far keep power under control in their Snapdragon designs without having to resort to a big/little and has thus been able to excel on the phone. So far, the Qualcomm strategy seems to be a winning one for phones in terms of both overall power savings and performance per miliwatt -- where on phones every extra hour of battery life is a cherished commodity. Such may not be true for tablets that can stand to have larger batteries and where performance at "some reasonable expectation" of battery life may be the more important.
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it's still lazy and ends up with juggling between the two cores, but that's not arms problem so they went with it.
but this is prett much the 4+1 core solution from nvidia anyways. it would be far better if they could just shut down parts of the one core to stop leakage. article blurb is just stupid though, it implies this would be a way towards cheaper, while it obviously isn't since it uses more die space.
Re:It's not necessarily ARM's solution (Score:5, Insightful)
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I'm glad someone else pointed this out. The OP's complaint makes it sound like we're going to run out of silicon if we use too much. Also the 'juggling between cores not being ARM's problem' bit doesn't make a lot of sense: ARM have an awful lot of interest in producing something that provides a real-world performance/power envelope that is attractive to their customers. If, due to the complexity of operating the chip or some other factors, this is not practical or possible, the chip won't sell. It's s
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It's suggesting that the likes of Samsung, Apple, HTC, Nokia, LG, Sony and many others just pick the chip because it had good marketing rather than a detailed analysis of the performance against the expected uses of the device.
Er, dunno if you'd noticed, but Apple actually rejected big.LITTLE. Apple used ARM's Cortex-A9 design in the Apple A5/A5X chips, but in A6/A6X, rather than upgrading to a big.LITTLE A7/A15 pair, they switched to their own custom ARM core design. It isn't quite as fast as A15, but supports a wider dynamic range of power/performance operating points (including A7-like power at the low end). As A15's max performance is only available at unsustainable (for tablets and phones, anyways) power consumption level
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it uses more die space
So? Transistors keep getting smaller. It's worth using more transistors to reduce power consumption. Also this isn't an either/or approach - other power saving tricks can be combined with this.
Moreover, "more die area" means nothing until quantified. How much smaller is an A7 than an A15? What portion of the die area of a SOC is an A7?
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Except it's easier in software to use big.LITTLE. If you wanted to switch from A7 to A15 and back, as
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Couldn't that be solved by adding Peltier junctions to cool the cores (albeit at a cost in battery life)?
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Yeah, too bad there's no way to have clock scaling and big/little on the same SOC.
Clock scaling is almost useless these days, power gating is where it's at.
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where on phones every extra hour of battery life is a cherished commodity. Such may not be true for tablets that can stand to have larger batteries and where performance at "some reasonable expectation" of battery life may be the more important.
This isn't directly for phones and tablets and it isn't "a lazy way out of the power problem".
We are not talking about a gradual increase in efficiency here, this is to solve the standby energy requirements for permanently powered consumer devices like TV-sets. (See the One Watt Initiative [wikipedia.org])
The first generation of devices that solved the problem had dual power supplies. One that was optimized for high efficiency for a low load. This was used to power a microcontroller that dealt with the remote control and s
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Lazy and effective is wiser than difficult and effective, every time. When you favour doing a clever design over adding a whole lot of cheap silicon you wind up with unreliable, hard to design, hard to build, hard to write-for monsters like the PS2 and PS3 architectures.
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Re:and... (Score:5, Insightful)
Nothing, except that Intel's most power efficient chips are in the same ballpark as the A15 (the power-hungry, fast 'big' chip) and they currently have nothing comparable to the A7 (the power-efficient, slow 'LITTLE' chip). And in the power envelope of the A7, an x86 decoder is a significant fraction of your total power consumption.
One of the reasons why RISC had an advantage over CISC in the '80s was the large amount of die area (10-20% of the total die size) that the CISC chips had to use to deal with the extra complexity of decoding a complex non-orthogonal variable-length instruction set. This started to be eroded in the '90s for two reasons. The first was that chips got bigger, whereas decoders stayed the same size and so were proportionally smaller. The second was that CISC encodings were often denser, and so used less instruction cache, than RISC.
Intel doesn't have either of these advantages at the low-power end. The decoder is still a significant fraction of a low-power chip and, worse, it is a part that has to be powered all of the time. They also don't win on instruction density, because both x86 and Thumb-2 are approximately as dense.
MIPS might be able to do something similar. They've been somewhat unfocussed in the processor design area for the past decade, but this has meant that a lot of their licensees have produced chips with very different characteristics, so they may be able to license two of these and implement something similar quite easily. Their main problem is that no one cares about MIPS.
Re:and... (Score:5, Informative)
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Covertrail is last gen tech. Its an iteration of the old atom. All intel CPUs up to "Haswell" were never designed from the ground up with power management in mind. It's all been bolt-on tech. These are Intels words.
Baytrail/silvermont;, coming out Q3 this year, will effectively erase any power advantage an Arm SoC. 22nm, designed from the ground up for power savings. 64bit. Quad core. Cheap. Intel fully expects to see sub 200 dollar windows 8 (Not windows RT) tablets.
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So, you're comparing an unreleased product that doesn't yet exist to shipping products and accusing me of spreading BS? And repeating claims that Intel has made about its last three generations of Atoms, which have never yet been true? Okay then, enjoy your bubble.
Oh, this made me laugh:
All intel CPUs up to "Haswell" were never designed from the ground up with power management in mind
The Pentium 4 was the last Intel chip not to be designed from the ground up with power management in mind, at least according to the chief architect of the P4 project when I spoke to him a little while ago.
The full Moore law (Score:2)
Rising defect densities have created a situation where — for the first time ever — 20nm wafers won't be cheaper than the 28nm processors they're supposed to replace.
The economic part is often left out on tech sites discus
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20nm wafers won't be cheaper than the 28nm
Won't be, or currently aren't? There's always the possibility of improved 20nm yields.
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It's still too early to declare the end of Moore's Law. If for no other reason, because very few fabs can produce 20nm chips, so nobody can tell if Intel made a mistake somewhere.
Yelds increse through all the life of a fab process, and those 18 monts aren't quite exact. We can still go back to normal.
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> I was once a programer when i was in High School. Since then I've noticed and been told friend who are programers/coders that programming languages now are sloppy when it comes to memory.
Garbage-collection performs better when there is more memory available, and many modern languages use garbage-collection. Then we have JIT, which requires a bytecode-compiler and a bytecode-interpreter to be in memory (unless you compile the whole program on startup). Basically we're trading memory for things like safe
wafer prices didn't go down for earlier nodes (Score:2)
Slashdot, I am disappoint (Score:2)
Came here for a companion cube analogy, leaving disappointed :(
ARM (Score:1)
just like air conditioning (Score:1)
The same strategy enabled high-EER air conditioning: use a small compressor which runs most of the time plus a larger one to handle peak cooling loads, rather than an even bigger compressor which cycles on and off frequently.