Hidden Debug Mode Found In AMD Processors 154
An anonymous reader writes "A hidden (and hardware password protected, by means of required special values in processor registers) debug mode has been found in AMD processors, and documented by a reverse engineer called Czernobyl on the RCE Forums community today. It enables powerful hardware debugging features long longed for by reverse engineers, such as hardware data-aware conditional breakpoints, and direct hardware 'page guard'-style breakpoints. And the best part is, it's sitting right there in your processor already, just read the details and off you go with the debugging ninja powers!"
Why... (Score:1, Interesting)
Security? (Score:5, Interesting)
I wondered the same thing - if these debug features are useful to developers debugging their own software, why not market this as a feature? The only thing that occurred to me, is that, maybe there is some sort of security problem with this debug functionality? Does anyone know - could these debug features be used to do something like break Operating System security models, leading to privilege escalation issues, or for other nefarious purposes?
Re:Security? (Score:4, Interesting)
It is possible that the debug features are for their internal use and they don't quite work as intended. They may be useful as such, but if there are implementation bugs that require cumbersome work-arounds on the software side, it may be that they are waiting for a non-buggy implementation before publically documenting the features.
It is also possible that they don't want to put the resources to documenting and supporting the debug features. After all, AMD is a small company compared to Intel and not that profitable. They even had some layoffs during the worst recession - what if they had to lay off the guys responsible for the debug mode?
Re:Security? (Score:4, Insightful)
Re:Security? (Score:5, Insightful)
it would put Intel up to create and release a debugging interface for their silicon.
Maybe Intel already has a debugging interface on their silicon. This AMD interface has remained hidden for who knows how many years, why couldn't the same thing happen with Intel? After all, it's not as if just anyone can reverse engineer a CPU.
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Indeed it is. [visual6502.org] And why not emulate it at the bare metal level in JavaScript, while you're at it?
Re:Security? (Score:5, Informative)
Re:Security? (Score:5, Informative)
Okay, the site's still down but I found a cache:
In fact, this is a fairly small incremental improvement over the existing hardware debugging support in x86 chips. It provides some extra control codes allowing the address in DR0 (one of the four registers i386 provides for hardware watchpoints) to do some slightly more clever things. For example, a watchpoint can be triggered on a partial match, rather than an exact match, to the address - this is really nice because it lets you put a watchpoint on the whole of any data structure that fits within a page. With the i386 watchpoints, you can only watch a single word with each register (4 words in total), while this means you can watch anything smaller than a page (and you can watch things bigger than a page by marking the page as no access, trapping the access, then unprotecting, single-stepping through the load / store, and continuing the process, which is how you implement watchpoints when you run out of debug registers).
Re:Security? (Score:5, Informative)
thank you (Score:2)
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Exactly, it's probably a bit of a kludge, and making it into a stable, documented, supported feature is going to be expensive with a lot of support and a small user base.
I have modes like this in some of my own products, and sometimes I'm leery of even having some other people on my own team have access to the debug modes, because of the potential for disaster and a WHOLE lot of handholding from me.
It's not worth the time it would take for me to set it up for broader use, and if I did, they would break thi
Re:Security? (Score:4, Insightful)
It is possible that the debug features are for their internal use and they don't quite work as intended.
Ding ding ding ding ... we have a winner!
I work for a processor design company. If this feature is kept secret, it's because the company does not want to put in the resources to make sure it works completely on every chip. It probably uses lots of hacks and violates the architecture in some obscure way. AMD does not want customers depending on this feature and then insisting that it works for future design wins.
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Except the UPS company makes that feature available for money. If AMD isn't releasing this info to anyone, then it isn't golden screwdrivering.
Re:Security? (Score:4, Insightful)
If there is some way to enable privileged instructions without using a privileged instruction it would completely circumvent operating system security.
Perhaps the slashdotted site answers this but I have to wonder why not just have a separate opcode to turn the debugging on?
Re:Security? (Score:4, Informative)
Perhaps the slashdotted site answers this but I have to wonder why not just have a separate opcode to turn the debugging on?
Because there's already a whole bunch of privileged MSRs that normal user code mustn't have access to - many of which are undocumented and processor-specific - so adding a few more is no big deal. Adding new opcodes, on the other hand, requires more work and risks them clashing with Intel's opcode choices at a later date.
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Adding new opcodes, on the other hand, requires more work and risks them clashing with Intel's opcode choices at a later date.
You mean like when they invented the 64 bit instruction set that intel is using today?
Re:Security? (Score:5, Insightful)
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Wasn't this the whole reason for microcode updates? To turn off or fix broken features.
Also, if it's triggered in userspace, the OS can block it.
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Also, if it's triggered in userspace, the OS can block it.
Not if your OS is rooted. Or root-kitted. Or both.
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Also, if it's triggered in userspace, the OS can block it.
Not if your OS is rooted. Or root-kitted. Or both.
That's already game over. If you own the OS, why would flipping the processor into a new mode help?
You already own the security system.
Re:Security? (Score:5, Interesting)
If flipping the processor into a new mode allows you to get out of the virtual machine and pwn the Host too, then yes it makes a difference.
Re: (Score:2, Interesting)
If an OS running on real hardware can block this call coming from user-mode then a hypervisor can block it coming from a VM. And if it can't be blocked you're p0wned either way. A virtual machine makes no difference.
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a) A VM config issue ( can talk to the host)
b) A bug in the VM software
c) A bug in the CPU or other hardware.
Whether this "Debug Mode" is equivalent to c) is what I'm talking about.
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Say you own the OS but it is in a virtual machine.
If flipping the processor into a new mode allows you to get out of the virtual machine and pwn the Host too, then yes it makes a difference.
Again, the VM host or hypervisor can easily block this exploit.
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You're assuming AMD doesn't talk directly to MS, VMWare, etc...
Re: (Score:3, Informative)
Not that I'm that knowledgeable about virtualization software, but I can't imagine that they would run priviledged code in the virtual machine as priviledged code on the host CPU, so it doesn't matter anyways.
In a VM running under hardware-based virtualization (AMD-V / VT-x) , privileged code in the guest generally does run at privilege level 0, also referred to as (privileged), kernel mode, or ultimate privilege. This is required to implement a protected mode operating system; a modern guest OS
uh what? (Score:2)
Since they execute your code directly on the host processor, they most certainly do work that way.
Re: (Score:2, Informative)
Not necessarily. Memory access can be blocked because the MMU controls what and where an application can write, transferring control to known code (the OS) on violations. Interrupts can be blocked because invoking them gives control to the OS. Priviliged instructions can be blocked because non-ring0 execution gives control to the OS.
The OS can't choose to block for example the "xor" instructions in any reasonable way. It's possible by basically single-step
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And notice how MOV DRx and RD/WRMSR are privileged instructions already.
Re: (Score:3, Informative)
IIRC, microcode updates are typically packaged as part of BIOS updates.
Tell me, how many PCs - as a percentage of those sold - get their BIOS regularly updated?
Re: (Score:3, Informative)
AFAIK they are packaged with every major linux distro out there, and I can't but presume that Windows ships with microcode patches as well.
Re:Security? (Score:4, Insightful)
Microcode updates for Windows machines are distributed through Microsoft Update and are downloaded and installed automatically if automatic updates is enabled (and it is enabled by default). No BIOS update required.
An example of such an update can be found by looking at Microsoft KB936357 [microsoft.com]
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Any CPU debug mode worthy of the name should be able to violate OS security six ways from Sunday...
Any security model worthy of the name would be agnostic to whether the CPU was in user mode or debug mode. While there is always the risk of a bug or a security hole, I can assure you that anything that goes into the chip goes in under the scrutiny of the security model. I know of many instances where some debug or test feature was not implemented because there was some potential threat to the security model.
Re: (Score:1, Interesting)
Re: (Score:2)
Does anyone know - could these debug features be used to do something like break Operating System security models, leading to privilege escalation issues, or for other nefarious purposes?
Exactly my thoughts as well. Perhaps if these features were documented, and compilers and kernels were written with these features in mind, they would be insanely helpful. This way, however, it's just a back door wide open.
Re: (Score:2)
Does anyone know - could these debug features be used to do something like break Operating System security models, leading to privilege escalation issues, or for other nefarious purposes?
Depending on how it is implemented, yes. Usually these operating modes require specific timing or hardware ports that are wired in silicon.
If they've got software overrides, possible timing chase conditions to trick timing, then yes, oh snap indeed.
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I guess this [slashdot.org] research is going to come in handy for some people if you're right. I'm hoping you're wrong though, the number of ways such an exploit could go wrong makes my head spin.
Re: (Score:2, Informative)
I used to work for a processor emulator tools company called Applied Microsystems Corp, Redmond WA. now defunct.
Up thru processors type 68040 emulations tools could be mounted external to the processor chip and performed the functions mentioned ( hardware breakpoints, memory maps, all register shadowing, soft and hard breakpoints, etc, all the things that you need to perform basic computer system development. As the complexity of the systems increased beyong those early 8/16/32 bit cpu, all those hardware f
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I only see three likely reasons: security (can't be secured), doesn't work (oops!), government backdoor.
I see at least one more: intended for internal testing, not guaranteed to work the same on all processors, AMD's not interested in guaranteeing that it works the same on all processors, and AMD's not interested in dealing with users whining that it doesn't work the same on all processors.
Re: (Score:2)
Such debug features circumvent any lower-level security completely.
Even if the debug features can only be enabled from hardware (avoiding the obvious malware risk), then existence of such features is fundamentally incompatible with existence of such issues as secure drivers (like HDMI encryption or copy checks on DVD's, securom style), DRM even by use of hardware dongles, etc.
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Anything to do with paging and interrupts could be a security vulnerability - some kernel processing has to go on in order to update process states. Being able to interrupt the process at the point just after getting kernel ring permission and before interrupts are disabled would be a dream, but probably just a theoretical one. Usually, it would be an atomic process, you couldn't do one without the other, but with these instructions, who knows...
Our OS theory courses covered early OS's which had a messed-up
Re: (Score:1, Redundant)
don't they reveal this to the users?
Probably because then they'd have to fully document the features and test them thoroughly on each new chip, which would likely cost them quite a bit more than developing the features in the first place.
They would also be saddled with supporting backwards compatibility in future chips, since it becomes hard to remove publicly-accessible features in a CPU once they've been added.
Yeah but ... (Score:1)
Just a matter of time... (Score:5, Interesting)
These exist on "all processors" as ways to test the processors and increase yield cheaply. The moment that the engineering samples go out, competitors get their hands on them, and it's only days or weeks before they figure out what's really going on. Kind of cat-and-mouse.
Re:Just a matter of time... (Score:5, Informative)
(As the original article was instantly slashdotted, I can only guess that the AMD exploit was found through software avenues.)
Re: (Score:2)
The Silicon Zoo [fsu.edu] website which shows what kind of artwork the layout engineers like to add to any unused area of silicon die..
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They never make any public info, but it's crazy what kind of logic blocks they find on silicon.
Sometimes scraping can tell simpler things, like an accurate estimate about how much profit a company is making on a chip, and thus how much money the company will have to invest in its next generation of chips.
Oops, slashdotted! (Score:5, Funny)
Apparently the debugging process doesn't help to combat the effects of a thorough slashdotting.
Re: (Score:3, Interesting)
yea, why stories continue to be posted with direct links instead of using things like coral cache is beyond me. If you KNOW the site you are going to link to can't handle a slashdot load then DON'T LINK DIRECTLY TO IT.
Of course this does not include sadistic evil people who enjoy watching websites crash and burn (probably a sizable but not large percentage portion of the slashdot community)
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I believe that's how it usually goes right?
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No kidding? Running debug mode doesn't speed things up?
I'm so patenting this secret to making Java speedy... then I'll own Oracle!
Coral Cache link (Score:1)
http://www.woodmann.com.nyud.net/collaborative/knowledge/index.php/Super-secret_debug_capabilities_of_AMD_processors_ [nyud.net]!
may not work until SOMEBODY uses the coral cache and is able to see the site (and thus cache it for the first time)
Re: (Score:3, Informative)
Try this [nyud.net]
Re: (Score:1)
SlashDot's link hygiene system doesn't recognize exclamation marks at the end of a URL as being part of the URL - notice that " [nyud.net]" has been inserted by /..
The ultimate security disaster? (Score:5, Insightful)
Re: (Score:1)
Haha, that would have been hillarious. All that security and someone compromising it with a simple 6letter pass :D
Re:The ultimate security disaster? (Score:5, Informative)
Not a security hole. This debug mode is not some kind of eleet hax0r backdoor. It's for debugging the processor and microcode.
It's the OS responsibility to ensure that normal applications can't simply do whatever they like directly to the hardware, including the CPU.
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It's the OS responsibility to ensure that normal applications can't simply do whatever they like directly to the hardware, including the CPU.
Unless of course the CPU is in a mode the OS doesn't know about.
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Ultimately it's the CPU which implements the security at the instruction and memory level. The OS only tells the CPU what code should run under which security context.
I suspect (Score:2)
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It's the OS responsibility to ensure that normal applications can't simply do whatever they like directly to the hardware, including the CPU.
Even though it's the OS's responsibility to ensure normal applications can't simply do whatever they want, the CPU needs to provide the necessary functionality. If the CPU allows writing to some register and provides no method of protecting that write, and that write causes anything that normally would not be allowed, then the OS can do bugger all about it.
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That's true, but irrelevant. The debug mode doesn't do an end-run around the machine's entire hardware and software security stack as so many posters were implying. By the time you have a chunk of executable code on your machine trying to set specific registers to specific values, all of the security measures in place up to that point have failed. Malicious code is malicious code and it does not need special access to some obscure CPU feature in order to do damage.
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Since TFA is down by now, and I can't get the exact details... does this mean that any program running and setting the right bits in the right registers can get "processor root" access to everything the processor does, irrespective of any security constraint the OS may place on that process?
Oh dear
Any program that can read and write to any processor register already has complete access to everything on your computer. The reason this is secret is not to protect your data, its to protect AMD's secrets.
Re: (Score:2, Interesting)
- The debugmode is worthy of its name, i.e. can bypass any ring and OS restriction
- It cannot be turned on or off in the bios or with a pin, since it is undocumented
- It is on by default
- The bit combination to set resides in usual working registers and can be triggered by usual computation by native code or in any bytecode interpreter (javascript, java etc.) of your choice when carefully targeting the
google cache of the article (Score:3, Informative)
Re: (Score:3, Interesting)
And the documentation about the new opcode is probably this one:
http://cbid.softnology.biz/html/undocmsrs.html [softnology.biz]
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No, TFA said (before it went down) that some registers have to be filled with defined values through hardware means to enter debug mode. In short, you won't stumble into it. And neither will any harmful software.
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Czernobyl == Polish Hacker? (Score:1)
To state the obvious: Chernobyl, or Czernobyl as is referred to in the polish language, is a very well known nuclear disaster site. Those crafty Polish are starting to make a name for themselves in the computer industry.
Re: (Score:1, Offtopic)
Chernobyl is in the Ukraine, not Poland.
Whoosh! Sure, the city is, but in this story we are talking about a hacker who lives in Poland who named himself after the infamous Ukraine nuclear disaster site.
hidden data-aware conditional breakpoints (Score:5, Funny)
So it's a software JTAG (Score:5, Interesting)
Re: (Score:1)
I'm just guessing, as the site is still inaccessible, but it sounds like this is a set of debug functionality beyond what you'd get with the normal debug registers or with a JTAG interface. AFAIK modern desktop/server processors still have JTAG interfaces (not just SoC, embedded type processors). Sure JTAG interfaces are often 'hidden' as you say... maybe there's a footprint there but you have to solder on some flying leads or a connector.. but without knowing about these new registers you still wouldn't be
Re:So it's a bit like a software JTAG, but not... (Score:1)
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I'd say password protected and undocumented is far more hidden than a unpopulated footprint marked 'jtag' (I know I know, not all hardware debug i/faces are always that obvious either :-)
But yeah, no one should be particularly surprised... these are ridiculously complex chips and would be impossible to develop and debug (the chip that is, not software for it) without extra hidden circuitry.
Re: (Score:1, Interesting)
It's not the same thing. Virtually every microcontroller has JTAG support and nobody would be surprised to find a JTAG interface in an embedded device. It would be very well documented in the datasheets. It's no big deal to find an unpopulated serial or JTAG header in a production device. These aren't manufacturer secrets -- they are well-known debugging interfaces provided for the benefit of the device developer.
AMD's proprietary debugging features are a different story -- features not intended for the
Some extra info, whilst the site is 'dotted... (Score:1, Informative)
http://webcache.googleusercontent.com/search?q=cache:EzsEFcoAZDAJ:www.woodmann.com/forum/archive/index.php/t-13891.html+amd+hardware+debugging+features&cd=5&hl=en&ct=clnk&gl=uk
Extensions for gcc/gdb (Score:1)
I bet (Score:1, Redundant)
Just an extension of existing debug facilities (Score:5, Informative)
Based solely on the Google cache of the forum post describing this (linked above), there's no need to go into hysterics. For hardware and systems geeks, this is very cool. It's an extension of the existing x86 debug registers (DR0-7) that allows you to set a debug watchpoint that only fires when specific data is loaded in.
There are a lot of researchers and tool builders that would love to have this because it would allow them to take a watchpoint fault whenever they only when they have a specific value from a specific location. For instance, let's say that every so often you get a null pointer exception at a specific address. However, if you current go into gdb and set 'watch 0x{address}', you're going to take a breakpoint every single time that pointer is accessed.. Wouldn't it be great to do something like 'watch 0x{address} NULL' and only stop your debugger whenever 0 gets written into that address?
That's what the forum posts imply, at least. "Guys, I've reversed this in part... breakpoints defined in DR0 can be made to fire only on data match (under optional mask), plus masking of any or all of 12 low address bits ! Works also for I/O break points, provided CR4_DE is set, of course !"
I would wager that this is not a large security concern. Access to DR7 is restricted to ring 0, and therefore enabling debug breakpoints must be done by the operating system. While extremely interesting (I wish I could read more!), Czernobyl appears to be describing a modification to debug breakpoints that are already enabled.
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Surely a good debugger can already do that...ie. When it hits a breakpoint it checks what value is being written and continues if it's not right.
The fact that this is 'hardware' doesn't seem like much of a win to me.
Re:Just an extension of existing debug facilities (Score:5, Informative)
Sure, but it's much faster to do it in hardware. This is the whole reason data watchpoints exist (See, for instance, the paper "Some Requirements for Architectural Support of Software Debugging" by Mark Scoctt Johnson from ASPLOS-I), as you could technically have your debugger put address & data checks around every memory access, but that leads to completely unacceptable overheads. It's faster to let the hardware check the addresses in parallel with regular execution and take a fault only if you touch the watchpoint.
Similarly, if the hardware will check the value before taking a debug interrupt to the kernel and subsequently signaling/scheduling of the debugger, it will be much, much faster than performing all that and then have the debugger check the address & throw this particular interrupt away before continuing execution. That constant interrupt cycle can cause 10,000x or more slowdowns if you're constantly accessing a value & taking bad watchpoints on it.
Re:Just an extension of existing debug facilities (Score:4, Insightful)
If you are an application developers, I would agree with you. Any decent debugger should allow you to set a conditional breakpoint, but I am not sure if you can say that for kernel debuggers which are very different animals typically.
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One of the best things about the windows operating systems is the kernel debugger! It can do all of that and more.
Re:Just an extension of existing debug facilities (Score:5, Informative)
Oh, and the summary's description, "hardware data-aware conditional breakpoints, and direct hardware 'page guard'-style breakpoints", matches up with the line I copied & pasted from the forum post. I previously described the "hardware data-aware conditional breakpoints"where you can make hardware take a fault if an address of a memory operation is matched && the value of the memory operation matches. Looking through my notes, embedded Power ISA (Book III-E) processors also let you set value-dependent watchpoints using the Data Address Compare (DAC) Registers. I'm not sure about other ISAs.
The second party of the summary's statement refers to to 'page guard'-style breakpoints. This is referenced by Czernobyl's "masking of any or all of 12 low address bits". Again, this is a very interesting extension of the x86 debug registesr, which only allow debug watchpoints of size 1, 2, 4, or 8 bytes (and the latter only in certain microarchitectures & modes) However, by masking out the low 1--12 bits of the address into don't-cares, it's possible to set watchpoints anywhere from 1-4096 bytes, limited to powers-of-two and size-alignment. This is cool from an x86 standpoint, but ARM, MIPS, and Itanium (off the top of my head) already do this.
Suffice it to say, the stuff that Czernobyl found is very cool in relation to x86, especially if these facilities were officially released to the public at any point in the future. However, it's very unlikely to cause any kind of AMD-only viruses or other scary security concerns. These features exist on other ISAs without any kind of world-shattering problems. :)
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If you can set a hardware breakpoint, then you can do the conditional in software, only slower. So this sounds like hardware acceleration, which is very useful, as it can make something go from way too slow to no speed hit at all.
Hardware easter eggs (Score:1, Offtopic)
Goodbye DRM!?!?!?! (Score:1)
Methinks this could be very useful in defeating many types of DRM. I'm thinking in particular DRM implementations similar to CSS, AACS, BD+, etc. Could this spell the end of DRM for once and for all? One can hope! Any experts care to elaborate (I'm no software developer nor a CPU engineer)?
This is not new (Score:2)
Remember Robert Collins and how he reverse engineered the ICE mode of old Intel processors?
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A 486FX? Wasn't that a 487SX?
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+0rc was one of the better ones, also. Very outdated nowdays but I still have a bunch of his tutorials around here somewhere...
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Offtopic? That's what you get when mentioning sites that closed when your average mod was a mere glint in the milkman's eye.
Re:Hidden? (Score:5, Insightful)
I can think of many reasons why it might be hidden. For example, it may be hidden because the cost of supporting it would outweigh the benefits of admitting the "feature" is there. I don't just mean in terms of documenting it and releasing that info for developers, I mean in termins of testing it for security reasons. Plus, let us say that a theoretical bug is found that creates a hole someone can exploit - is it patchable? It's a whole can of worms AMD may be right to avoid opening.
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And how do you know some top black hats don't already know about this for years and have already exploits for it? It's a classic example of security through obscurity.
If it's not safe (and if it's baldly tested, it is), I'd expect AMD to disable it on a physical level, not leave it there "hidden" for someone with poor intentions to find out.
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I can think of many reasons why it might be hidden. For example, it may be hidden because the cost of supporting it would outweigh the benefits of admitting the "feature" is there. I don't just mean in terms of documenting it and releasing that info for developers, I mean in termins of testing it for security reasons.
...and, if it's documented as an architectural feature rather than a feature of a particular processor or line of processors, guaranteeing that it works the same in future processors, even if they have a different microarchitecture. (And even if you explicitly document it as a feature of a particular processor, if you don't implement it the same way in your next generation of processors, somebody will probably have ignored the "this is a feature specific to the Phenom 666" note in the documentation and wri
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My question is, is this actually hidden? Stuff like this is usually in the data sheets. So, does anyone have access to the actual processor data sheets? I didn't find them on AMD's site, just stubs containing the first few pages.
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That is not always the case.
For example they did not properly document and release the docs on the hardware RNG in their first chipsets when it came out. As a result it ended up supported only on Linux on a "friend-of-mine" basis and MSFT (on whatever basis). The other OS developers did not know about it for a while (more than half a year). I remember personally telling Theo De Raadt on BUGTRAQ at the time to stop talking rubbish that AMD does not have a hardware RNG and he was genuinely shocked. However th