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Hardware Technology

A Brief History of Chip Hype and Flops 275

On, Brooke Crowthers has a review of some flops in the chip-making world — from IBM, Intel, and AMD — and the hype that surrounded them, which is arguably as interesting as the chips' failures. "First, I have to revisit Intel's Itanium. Simply because it's still around and still missing production target dates. The hype: 'This design philosophy will one day replace RISC and CISC. It is a gateway into the 64-bit future.' ... The reality: Yes, Itanium is still warm, still breathing in the rarefied very-high-end server market — where it does have a limited role. But... it certainly hasn't remade the computer industry."
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A Brief History of Chip Hype and Flops

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  • by Prodigy Savant ( 543565 ) on Monday February 16, 2009 @03:57AM (#26869929) Homepage Journal
    If AMD hadn't rushed with their 64 bit version of the x86, about now, itanium would be getting popular and hence cheap.
    Market forces have so much to do with technology advancement. A lot of times, superior technology has to take a back seat ...
    • by hannson ( 1369413 ) <> on Monday February 16, 2009 @04:03AM (#26869947)

      I don't know enough about the architectures to say which one is better (x86-64 vs IA-64) but backwards compatibility with x86 is a big win for x86-64.

      • by wisty ( 1335733 ) on Monday February 16, 2009 @07:07AM (#26870699)

        It didn't help that part of the advantage of IA-64 was that it let programmers write their own branch prediction. Which they didn't want to do.

      • IA-64, iirc was slower than x86 when compiled with primitive compilers (read gcc).

        A lot of the advancements were in floating point, which is still meaningless to most people except gamers (which wouldn't be using the platform) and special interest companies. Namely, branch-prediction's were more accurate for instructions which take 32 to 64 clock-ticks (64bit sqrt, divide, etc).

        The advancements of the VLIW were negated by very-large prefetched instructions with cached pre-compiled op-codes.

        The branch predictions only gave you a theoretical advantage over the very large branch-prediction buffers, and in some circumstances the branch-predictors gave you better decisions (hot code could pre-guess a direction before a predicate register was even populated - the Itanium would have to execute both paths, but the branch-predictor choose the hottest path). Further Alpha laughed at Itanium, saying they've had branch-prediction hint op-code variants for years(without predicates), and they showed many synthetic algorithms which would produce better alpha code than Itanium.. Basically saying for most algorithms, predicate-registers produce less efficient code than other alternatives (just happens that x86 didn't have any such instructions - but that would have been easy to correct with yet another op-code prefix). Note i686 did introduce the conditional move instruction, which goes a long way to small but common branch avoidance.

        Register windows (a la sparc's) are a neat idea, but with register renaming on the x86, a tight function-call loop can be just as fast. Plus the spilling of registers into memory often is mitigated with the high speed cache. Further, many arguments against the small register set of the x86-32 are avoided in the x86-64's much larger register pool. Lastly, if you only have 16 registers (of which only 8 are hot), then you can efficiently utilize a pool of 256 rename-registers. If, however, you have an explicit 128 register addressibility (most of which is statistically cold), it's difficult and inefficient to remap them in future versions of the architecture. Note that every power of two register-size causes slow-downs in register interconnects - to say nothing of the real-estate and power-drain.

        Then there's the fact that a program that only needs 2Gig of RAM will generally work better in 32bit than 64 due to the half-sized mem-pointers. More fits into your cache. Note other unrelated optimizations in x86-64 may counter-balance this (though this is independent of the 64bit design), so YMMV. I know that SUN's JDK 32bit runs faster, more smoothly than the 64bit version for most of our apps. Yes there are some CPU instruction optimizations for x86-64, but memory in java tends to be the limiting factor.. The same server app will consume 400Meg on a 32bit version and sometimes breaks a gig on the 64bit version. The GC times are measurably slower.

        The explicit register rotation used in tight-loops - allowing a 6 op-code loop to execute every op in every stage of the loop, thus degrading a loop to at most n clock cycles is nice in theory. But what if your loop is more complex than a trivial inc/dec. And what if you need one more op-code than the architecture supports? Moreover, there's no technical reason why a CPU can't detect such a loop after k iterations and allocate register-renaming to do the exact same thing. With a hot-spot detector (part of branch-prediction), a subsequent access could fire up the loop immediately. But more importantly, future versions of the CPU could support even larger loop-lengths, as you're not explicitly limited by the bit-lengths, or the originally staticly compiled code.

        The sad part is that the explicit compilation of CPU hints, and minimization of register spilling that are the hall-marks of the Itanium should theoretically lead to a slimmer, lower-power, higher-theoretical-clock CPU.. But due to other engineering decisions, the exact opposite is true. Lower clock, bigger silicon, higher power.

        Basically th

    • by Jurily ( 900488 ) <<moc.liamg> <ta> <yliruj>> on Monday February 16, 2009 @04:09AM (#26869973)

      I don't think so. x86-64 is fully backwards-compatible with x86. Itanium is not.

      Wanna guess why they're not that popular?

      • by snowgirl ( 978879 ) * on Monday February 16, 2009 @04:15AM (#26870001) Journal

        I don't think so. x86-64 is fully backwards-compatible with x86. Itanium is not.

        Wanna guess why they're not that popular?

        You don't know the architecture? The first Itaniums had hardware x86 processors. The only reason they don't now, is that it was found to be faster to emulate the x86 than run it with a diminished hardware.

        • The first Itaniums were pretty much a dismal failure...
          They ran at around 800mhz, so clocked lower than x86 systems of the time which were around 1.4ghz if i remember (and the mhz myth still very much alive, with intel fuelling it using the p4)... Their x86 support was roughly the speed of a p90 and therefore of little use beyond running one or two small legacy apps.
          In terms of outright performance they were behind Alpha and Power at the time, so much for this new architecture. And when it came to price and power consumption they were behind everyone else.

          When Itanium2 came around it performed a lot better, still guzzled power, and they realised that software emulation of x86 was faster than the hardware support, other than that the chips were still too expensive for what they were.

          Now, Itanium is pretty much relegated to the high end niche that Alpha occupied before it was canned.

          Itanium suffered from end users being locked in to proprietary binary only software - which only the original vendor could port... Some were unwilling, some didn't see the business case, some demanded that HP/Intel fund the porting, only they couldn't fund everything, so Itanium is left with a very limited set of apps...
          OSS support was better, but it suffered from the high cost and rarity of the hardware, in that hobbyists had little chance of getting hold of the hardware to play with.

          Personally i think HP/Intel would have been better off putting the effort into continued development of Alpha... It already had a software and user base, it already had x86 emulation which performed reasonably well, and it had a legacy behind it of old hardware that was cheaply available to OSS developers. Even today, Alpha versions of Linux seem far more active than the IA64 versions... Plus any customers already using Alpha would not have needed to migrate (and many of them migrated to Sun or IBM).

          • by anothy ( 83176 ) on Monday February 16, 2009 @08:40AM (#26871095) Homepage
            HP/Intel would have done better, technically, to work on Alpha, but they couldn't sufficiently dominate the market for their tastes in that case. half the point was to have something that they controlled, and Alpha, while technically great, was already too widespread for that.
            which, really, is the most important response to the original parent's point. what was AMD supposed to do, sit around while Intel dictated what the terms of the next stage of the market would be? what gives Intel some inherent right to that sort of dominance? AMD did exactly the right thing, from a business perspective: they saw what they believed to be a strategic mistake that left a market hole open, and produced a product to fill it. turns out they were right.
            turns out it was the right thing to do technically, too. when Itanium hype was at its peak, i remember lots of actual engineers i knew (and even some subset of the tech press) pointing out that EPIC was really just tweaked VLIW, and that had been tried and failed a few times. amd64 has consistently outperformed IA64.

            even the quote in the summary is misleading. yes, IA64 is still plodding along in the high-end server market, but it's even an also-ran there. POWER and amd64, in particular, continue to trounce it, both for your normal "server" market and for the really high end scientific cluster stuff (it's got, what, one spot on the top500 list?). it's a pretty substantial failure, really all around.
          • Now, Itanium is pretty much relegated to the high end niche that Alpha occupied before it was canned.

            All I know about iTanic sales is that the only customer I know of was unwilling. Yuba College in Marysville used a 4-way alphaserver to handle the system on which their student information is kept. The upgrade path for that software after the death of the Alpha was to go to iTanic. So they now have an 8-way iTanic2 server to do what? Some database shit, basically. Run HP-SUX. I used some of the extra horsepower to implement ipsec to the windows clients for them, but it's still a massive overkill and a massi

    • by learningtree ( 1117339 ) on Monday February 16, 2009 @04:16AM (#26870009)
      The biggest advantage of AMD x64 over Itanium is the ability to run x86 32-bit code natively without any performance penalty.
      The comparison is not just about better technology. Think of the trillions of lines of x86 32-bit code that has been written.
      Would you render all this code unusable just because you want to move to a better architecture.
      • > Would you render all this code unusable just because
        > you want to move to a better architecture.

        Yeah, and I'd put Debian on that machine.
      • Very little code is written in x86 assembly, the vast majority is written in higher level languages and then compiled or interpreted... When you have the source code, porting it to IA64 is relatively easy. Look at Linux, it runs on a variety of architectures, as do a huge number of applications. Many of the original authors of those apps would never have considered they might be running on IA64, Alpha, Arm, Mips or Sparc someday...

        The problem is software being delivered as binaries. Binary software distribution is holding back progress, making it necessary to continue supporting old kludgy architectures instead of making a clean break to something new and modern.

        • Re: (Score:3, Interesting)

          by itsdapead ( 734413 )

          The problem is software being delivered as binaries.

          I think that's chicken-and-egg: if you have a single, dominant, binary-compatible architecture then the most efficient way to distribute commercial software is as pre-compiled binaries.

          Linux runs on so many architectures for the simple reason that many Linux developers take a pride in their work and actually care about interoperability: all that cross-platform support doesn't happen magically because its written in C! A substantial app will be riddled with "#ifdef IA32/#ifdef MIPS"-type, and if you compile

    • by TheLink ( 130905 ) on Monday February 16, 2009 @04:18AM (#26870017) Journal
      The Itanium is not superior at all.

      Even before the AMD64, the Itanium was only good at mainly contrived FPU benchmarks. It was dismal in integer performance.

      When you didn't care about x86 compatibility and wanted to spend lots of money for the usual reasons, it was better to go with IBM's offerings like POWER (which is still a decent contender in performance).

      Intel couldn't offer you much else other than the CPU. They had to rely on HP, who just left their Tandem and VMS stuff to rot. Yes there were other big names pretending to do Itanium servers, but in practice it was HP.

      The Itanic was an EPIC failure.
      • Re: (Score:3, Interesting)

        by BikeHelmet ( 1437881 )

        Didn't the Power6 have insane FPU performance? Double that of its contenders?

        I think it still beats every CPU out there. (FPU only)

        I remember seeing benchmarks where a 4 core Power6 beat 8 Xeon cores and 8 opteron cores, by a safe margin.

        But those things are so huge... at the time of release, they were bigger than all GPUs. :P Lots and lots of transistors, and lots of ghz.

    • Re: (Score:3, Informative)

      by anss123 ( 985305 )

      If AMD hadn't rushed with their 64 bit version of the x86, about now, Itanium would be getting popular and hence cheap. Market forces have so much to do with technology advancement. A lot of times, superior technology has to take a back seat ...

      Perhaps, but how superior is that superior technology?

      The idea with Itanium was to make a CPU that could perform on the level of RISC and CISC CPUs with a relatively simple front end. In essence the Itanium executes a fixed number of instructions each cycle, then leaves it to the compiler to select which instructions are to be executed in parallel and make sure they don't read and write to the same registers and such (instead of having logic in the CPU figuring this stuff out).

      It was a neat idea, but a

      • Re: (Score:3, Insightful)

        by Hal_Porter ( 817932 )

        The idea with Itanium was to make a CPU that could perform on the level of RISC and CISC CPUs with a relatively simple front end. In essence the Itanium executes a fixed number of instructions each cycle, then leaves it to the compiler to select which instructions are to be executed in parallel and make sure they don't read and write to the same registers and such (instead of having logic in the CPU figuring this stuff out).

        Actually you could see that Itanium was in deep trouble when it launched at a lower clock rate than x86. The whole idea behind EPIC "explicitly parallel instruction computing" was that you move instruction scheduling to the compiler, and that allows you to essentially out-RISC RISC, i.e. build a dumber chip that can be clocked faster. I think you're right about technology too. Back in the CISC vs RISC days an R4000 for example could be clocked faster than a 486 due to its ultra streamlined pipeline - MIPS o

        • by Bert64 ( 520050 )

          IA64 wasn't so much about clock rate, as theoretical instructions per clock...
          Rather than having multiple cores, the idea was a sort of SIMD throughout the processor... But relying on the compiler to generate optimal code...
          Assuming you have optimal code, an Itanium should be able to get a lot more work done in a single clock cycle than any x86 chip.

    • Re: (Score:2, Funny)

      by Anonymous Coward

      Boohoo! AMD is being so *mean*! They're *competing* with us! It's just not *fair!

    • no the main problem is proprietary software. the amd64 could establish itself because it supported the existing proprietary software. it would be interesting to know what percentage of x86-64 systems are still running 32-bit software exclusively. i'd estimate about 90%. the reason? broken or missing flash for x86-64, broken or missing windows, broken or missing microsoft office, broken or missing photoshop, broken or missing autocad etc.

      free software has the advantage that, if you aren't embedding assemb
      • It's a *little* harder than that... you have to worry about endianness, alignment issues, word sizes, etc. and these do affect higher level languages. Compiling for new architectures - even on code that's been compiled on other architectures before (if it hasn't, chances are it'll need modification) - is more than a simple recompile.

  • by Anonymous Coward on Monday February 16, 2009 @04:09AM (#26869975)

    How could the writer blatantly ignore the 486sx, the winchip, or the original (cacheless) Celeron??

    Although, I've always contended that TI's 486dlc (which fit in a 386 socket) was one of the worst chips I ever used, it overheated, lacked full 486 compatibility, and froze up the system with random halts whenever I needed to get something done on it!

    • Re: (Score:2, Insightful)

      by Cprossu ( 736997 )

      AC how could you have forgotten to mention the socket 4 Pentiums, or the K5 on AMD's side, the Transmetta Caruso, the Cyrix MII, or the slot 1 PIII 1.13?? From the extraordinary cost alone, you could have also called most of the intel overdrives a flop too.

      although the winchip (shudders) I hope no one was unlucky enough to have to depend on a box with one of those running it

    • Re: (Score:3, Interesting)

      by anss123 ( 985305 )

      TI's 486dlc (which fit in a 386 socket) was one of the worst chips I ever used, it overheated, lacked full 486 compatibility.

      What app did you run that needed full 486 compatibility? Being able to plug a 486 into an old 386 mobo seems like a neat idea, and any software that ran on that 386 would of course run on the nerfed 486 right?

      Too bad about the overheating though.

    • by drsmithy ( 35869 )

      How could the writer blatantly ignore the 486sx, the winchip, or the original (cacheless) Celeron??

      The 486SX was hardly a flop, they _very_ well.

    • by level_headed_midwest ( 888889 ) on Monday February 16, 2009 @12:18PM (#26873231)

      I am surprised that they knocked the AMD Puma in the article while leaving the following piles of crap unmentioned:

      1. The original Covington Celerons with no L2 cache
      2. Original Pentiums with the FDIV bug
      3. The Pentium III Coppermine 1.13 GHz that was infamously unstable
      4. Socket 423 Pentium 4
      5. The Pentium 4 Prescott 3.6 and 3.8 that overheated and throttled at stock speeds on the stock heatsink

      All of those chips were bigger duds or had bigger errors than even the TLB error in the BA/B2 Barcelona Opterons they mentioned in the "Part 1" article.

  • What about ACE? (Score:4, Insightful)

    by Hal_Porter ( 817932 ) on Monday February 16, 2009 @04:10AM (#26869981)

    Back in 1999 the ACE Consortium had Compaq, Microsoft, MIPS Computer Systems, DEC, SCO, and a a bunch of others [].

    The plan was to launch a MIPS based open architecture system running Windows NT or Unix. Back then the MIPS CEO said MIPS would become "the most pervasive architecture in the world". The whole thing fell apart as Compaq defected, MIPS run out of cash and got bought by SGI. Dec obviously moved to supporting Alpha instead. Microsoft shipped NT for MIPS, Alpha and PPC for another few released and then gave up the ghost.

    • Re: (Score:3, Informative)

      by anss123 ( 985305 )

      Back in 1999

      Back on 1991 you mean?

      I only know about that since it was mentioned in an article describing boot.ini. It was from an age before the web so I guess only those who bought certain dead tree magazines ever heard of it.

    • by Bert64 ( 520050 )

      Similar thing happened with PowerPC, it was going to be the next big thing... Apple came on board, Microsoft made a version of NT for it, Sun ported Solaris to it...

      Motorola's m68k was the last big thing, so they assumed everyone would follow their migration path to PPC... Instead, most players dumped Motorola. They could have extended m68k like Intel has done with x86, the result would still have been messy but not as bad.

      • Re: (Score:3, Interesting)

        by anss123 ( 985305 )

        They could have extended m68k like Intel has done with x86, the result would still have been messy but not as bad.

        Don't be too sure about that. The good old m68k had some instructions that gave CPU designers headache at a glance :-) On the 68060 they literally dropped a number of commonly used instructions outright, don't think Intel ever did that, and with the Coldfire descendant they dropped so much that it's not possible to write a "Coldfire.libary" like Amiga users did for the 68060.

        By luck or by wisdom, x86 avoids the hardest problems normally associated with CISC.

      • They did, for a time. It was called the 68060 and had Pentium like features. But it was too late and they didn't bother raising clock speed later on.
  • That's it? (Score:5, Insightful)

    by Anonymous Coward on Monday February 16, 2009 @04:18AM (#26870011)

    A short paragraph about Itanium (or, as the Register likes to call it, Itanic)? A few brief paragraphs about PowerPC? A few brief paragraphs about Puma?

    Come on. There's a lot more scope for this sort of article. What about Rock [], promised three years ago, with tape out two years ago, and yet we're still waiting for systems? What about the iAPX 432 []?

    You've got the basis for a good article, but dear $DEITY, flesh it out! There's more meat on Kate Moss than on this article!

    • Re:That's it? (Score:4, Insightful)

      by Hal_Porter ( 817932 ) on Monday February 16, 2009 @05:26AM (#26870281)

      He'd be better off structuring the article as quiche eaters (computer scientists) vs hardware designers.

      Hardware designers try to build something which can be clocked fast. They don't care if it's aesthetically pleasing and so on.

      Quiche eaters moan about how limited von Neumann architectures are. They try to do a CISCy things like reduce the abstraction level between the programmer and the instruction set with lots of hard to implement features in the instruction set, and design ISA where it is impossible, newspeak style, to write incorrect code (e.g. segmentation or capability based addressing []). The hardware engineer way to do this is a TLB and page table.

      x86 has had input from both camps, but back compatibility has limited the damage the quiche eaters can do. In the end most of the quiche eater features end up unused (e.g. segmentation and complex instructions) and you end up running ugly, primitive but very fast instructions translated to run on Risc core. It kicked the ass of the quiche eater designed iAPX432 and Itanium.

      Of course the dequicheffication of the x86 was to some extent triggered by competion from the very low quiche Risc chips. In fact MIPS did memory protection by implementing only a TLB in hardware, TLB writes and the rest of paging was done in software. Of course, sometimes RISC designs are so fundamentally anti quiche that the very fundamentalism is form of quiche eating, like Sparc's multiply and divide step instructions that ended up being slower than the 68K's full multiple and divide instructions.

    • i dunno enough to be sure, but reading part 1 leads me to two conclutions:
      1.) The guy really hates the itanium

      Advice for AMD: Hold the superlatives. First deliver in quantity the actual, viable physical chip that's supposed to do all these things better than the shipping Intel chip (shipping since October 2006). The adage "talk is cheap" has special meaning to journalists. And, I would imagine, special meaning to AMD's waiting customers.

      The guy doesn't get marketing stratergies, talking up something that is late in a market your loosing is simply a holding tactic so that people don't run into the hands of the competition.

      • The AMD chips are still cheaper, so what if you can build a faster computer with intel chips? The average user isn't going to do nuclear blast modeling anyway. They'd do fine with a netbook with a 1.6GHz Atom, probably for the rest of their life if it wouldn't break.

    • Re:That's it? (Score:4, Interesting)

      by TheRaven64 ( 641858 ) on Monday February 16, 2009 @09:54AM (#26871535) Journal

      The iAPX was a beautiful design, and so typical of Intel. That, the i860, and the Itanium all have the feel of chips designed by theorists. Gorgeous on paper, horrendous on silicon (although the i860 did quite well as a GPU. High-end NeXT stations used them to run the Display PostScript engine).

      A former Intel Chief Architect told me a story a couple of years ago about a chip that Intel was making when he went for his Interview. Apparently they'd heard about object-orientation and thought it would take over the world, so they started designing a chip for pure OO languages. This chip supported boxed integer values in hardware so everything really was an object. The problem came when they started to work on the compiler. Most operations required shifting pointer values right by four. Unfortunately, no one had thought to make a fast way of producing constant number objects. You needed a 200-cycle sequence to do this, which made the whole system so slow it was unusable for code written in high-level languages.

    • iAPX 432 (Score:4, Funny)

      by nurb432 ( 527695 ) on Monday February 16, 2009 @10:00AM (#26871585) Homepage Journal

      Was so far ahead of its time, we still are not ready for it. Tho finally silicon has advanced far enough to make the architecture work.

      ( note my nick.. you can tell i was a fan :) )

  • by ausoleil ( 322752 ) on Monday February 16, 2009 @04:22AM (#26870045) Homepage

    Reading through the article, it seems that other than AMD's Puma, most of these failures have one thing in common: they are not backward compatible with the chips they replace.

    People are loathe to buy a new computer and all-new versions of software to run on it. Look at the 64-bit Windows architectures. How many folks are running 32-bit software on those?

    Bottom line is that the software IS the computer and the chips ultimately are sexy only to EE's and gearheads.

    • Do you think that the i7's new socket will prove to be a barrier to upgrade?

      I recently had to get a new motherboard, and the combined cost premium of an i7, taken over the processor and motherboard, was far too high to even consider. I could have bought three computers for it!

      • by anss123 ( 985305 )

        Do you think that the i7's new socket will prove to be a barrier to upgrade?

        Nah. CPU only upgrades are actually pretty uncommon. New CPUs often require new FSB speeds and lower voltages so you'll end up having to change the mobo anyway.

        Don't buy a mobo thinking you get to update to a much faster CPU later on - unless you buy a slow ass Celeron today and snag a cheap Extreme Edition of eBay in a few years (and even then you might be better off with the slow ass Celeron of the future :-)

        • by cowbutt ( 21077 )

          I've had mixed luck with CPU-only upgrades.

          I've got a 440BX Asus P2B machine that went from a PII-266 in 1998, to a Celeron 500 in about 2000, and a PIII-450 in about 2003. I've also got a i845PE Gigabyte GA-8PE667 Ultra which went from a Celeron 1.7GHz in 2002 to a P4 2.53GHz in 2008. On the other hand, I've had two machines that I've never upgraded the CPU on because the upgrade path disappeared, or simply wasn't economic.

    • lack of chip-level backwards compatibility is an issue, but not a deal breaker. that can be reasonably managed, and has in plenty of cases you can point to without trying too hard. these examples failed to deliver on their promise for entirely unrelated reasons.

      look at the examples given, and you'll see compatibility wasn't really a factor for the first two, either.
      Itanic had explicit backwards compatibility, at first in hardware (through the use of a separate embedded core), then in software. that compati
  • AMD's 4x4 Quad-FX dual socket motherboards were also a flop. AMD's line of FX-7x series processors for these boards were a limited run. Now considered collectors items. If you can find them! Intel's Skulltrail, was much hyped, but it is now very much quietly pensioned off by Intel, although it a few more boards sold than 4x4.

    Anyway where are the Mandatory FLOP puns I was expecting? (Considering this is a brilliant set-up by article poster)

    (Mandatory wiki linkage: []
  • Nice title... (Score:2, Insightful)

    by V!NCENT ( 1105021 )
    I just got out of my bed 2 minutes ago and by vaguely reading the word FLOP I thought about Floating point Operations Per Second...
  • by m.dillon ( 147925 ) on Monday February 16, 2009 @04:31AM (#26870081) Homepage

    It turns out that the cost of a translation layer has become irrelevant as chips have gotten faster. It's not even considered a pipeline stage any more, not really. That is, it is no longer a bottleneck to have to have a layer of essentially combinational logic to convert a CISC instruction set into a mostly RISC / VLIW one internally. This savings grace is also why the fairly badly bloated intel instruction set no longer has any real impact on the performance they can squeeze out of the chips.


    • I think we still pay a price. My laptop could easily heat to 60-70'C when doing CPU-intensive stuff.
    • by drinkypoo ( 153816 ) <> on Monday February 16, 2009 @08:49AM (#26871137) Homepage Journal

      "Bloat" is not the problem with x86. The problem is that there are zero general-purpose registers - many instructions require that the operands be in specific registers, which blows the whole idea of general-purpose registers right out of the water. This is compounded by the fact that there are only four registers which you could even call general-purpose with a straight face. You can sometimes use some of the others (if you're not using them for anything else, and sometimes you have to have pointers in the pointers) to stash something but they're not useful for computation. Just taking an existing program and recompiling it from x86 to x86_64 with any kind of competent compiler will result in a significant performance improvement, often pegged around 10-15% just due to avoiding register starvation issues. While register renaming somewhat mitigates the issues with the "general" purpose registers in x86, it does not eliminate them entirely.

      On the flip side, x86's variable instruction lengths result in smaller code which can improve execution time on massively superscalar processors simply by virtue of getting the instructions into the processor faster.

  • Transmeta Crusoe? (Score:5, Insightful)

    by Jeppe Salvesen ( 101622 ) on Monday February 16, 2009 @04:47AM (#26870127)

    That definitely belongs in there. Sorry, Linus.

    • Re: (Score:3, Insightful)

      by paul248 ( 536459 )

      From what I've heard, Transmeta was creating some pretty remarkable CPU technology; they just made a series of awful business decisions.

  • AMD still won't openly admit this but there's a timing problem with all or at least most of their Athlon X2s where the cores' clocls get out of sync with each other. That causes major graphics problems in games that rely on it like Runescape and Halo 2. It also causes really strange side effects where basically the computer gets slower and less responsive over time until you restart it. I never knew what was wrong with my computer and assumed it was inefficient software but then I heard about this and OM
    • by Rockoon ( 1252108 ) on Monday February 16, 2009 @05:41AM (#26870345)
      You are uninformed. The AMD multi-core "problem" is a software problem.

      People who programmed for single-core systems assumed that the processors internal tick count, called the timestamp counter (read with the RDTSC instruction), would be monotonically increasing. The fact is that each core could have its own timestamp counter and if a process is migrated to another core by the OS scheduler, then the monotonically increasing assumption falls flat (time can appear to run backwards.) This is true for AMD multi-core processors as well as ALL (AMD and Intel) multi-processor setups.

      The AMD patch does several things, one of which is to instruct windows to not use the timestamp counter for use in its own time-keeping. Windows XP defaulted to using this timestamp counter for timing, because both dual-core and multi-cpu systems essentially didnt even exist when it was released. This is accomplished by a simple alteration to boot.ini telling windows to use PMTIMER instead of its default.

      Any modern games that are not fixed by the above patch were programmed by stupid people. Thats right... Stupid. They are accessing hardware directly rather than going through a standardized time keeping layer. Their assumptions about time are wrong when using RDTSC, because it isnt a time-keeper. Its a tick counter specifically associated with a CPU (Intel/AMD) or CORE (AMD)
      • by TheThiefMaster ( 992038 ) on Monday February 16, 2009 @06:55AM (#26870657)

        A slight correction: Multi-processor systems had existed for a while, but dynamic clock speed scaling was new, and it was THAT that threw out the use of RDTSC as a timer. The problem just got more obvious when multi-socket chips were introduced that could change speed independently.

        With a single chip that could adjust clock speed dynamically (based on load) the problem with using rdtsc wasn't too bad, because most games were (and still are) written to thrash a CPU (core) to 100% load anyway. However with two cpu (cores) in a system, one core could slow down while the other was running full-tilt. When this happened the tick counts would get out of sync. If the program using rdtsc then got scheduled onto the other cpu, it would see time as having jumped forwards or backwards.

        It's worth noting that running different speed CPUs in a dual-socket board was possible before dynamic frequency scaling, as long as the FSBs matched. I accidentally had a 2GHz and a 600MHz cpu (133MHz FSB IIRC) in dual socket-A board at the same time once, and aside from horrifically confusing the dedicated server I was running on it, it ran fine. Not only were the rdtsc readings out of sync, causing it to keep thinking it had jumped into the past or future, but they were running at significantly different rates, causing it to keep switching between real-time and slomo or super-speed!

    • It also causes really strange side effects where basically the computer gets slower and less responsive over time until you restart it.

      I've had this problem with Intel systems, too, ever since I started working with Core Duo machines. I can't offer any insight, but I noticed right away that on multiple computers, the GUI of every program on WindowsXP noticeably slows down during the course of an hour. Benchmark performance doesn't seem to be affected, but responsiveness slows down a LOT. The good news is, restarting the affected program fixes the problem -- a Windows restart isn't needed. I've only seen this problem on dual core system

      • by wisty ( 1335733 )

        You can probably play around with the affinity, so that the process only runs on the one core.

  • by Anonymous Coward on Monday February 16, 2009 @05:35AM (#26870323)

    I worked on Itanium/Merced. Keep in mind I was mid-level (not high enough to see the good political fights first hand, only getting the after effects). Below is my opinion from what information I saw or collected at the time. Take it or leave it as you will.

    Itanium (or I-Tanic) was supposed to be the P7, back when Intel still used P#s for chips. That Pentium 4 was never supposed to exist. Basically, Itanium was so bad, the Portland design teams came in a ate the Santa Clara team's lunch.

    The biggest problem for I-Tanic was management, on many levels.
    1) No good top guy
    The main and original project lead was more focused on marketing and "the platform" than actually making the chip. So, there was no top leadership at the CPU design level. This allowed the "lieutenants" to squabble among themselves (more later).
    They finally got a good guy in (who's name I hate to say I forget. It was a long time ago). I believe he had done Kalamath. The project was in a never-ending re-design spin at this point. When he was there you knew there was a Captain of the ship. You weren't 100% sure he was sailing in the right direction, but felt things were moving ... finally. He lasted about 3 months, until his wife (supposedly) gave him the "me or CPU design" ultimatum. He then moved up to start the Intel DuPont site (which was supposed to be as big as the Portland cite). That didn't work out so well for him.
    His hand-picked successor lasted about 1 week before "family reasons" caused his resignation. I assume he looked at the state of the now 2 year delayed chip and ran.

    2) boom & Silicon Valley
    The "lieutenants" didn't give a rat's ass about the project. It was mostly a "pump and dump". Being the boom and in Silicon Valley, their main concerns were taking over ownership of a "cluster" (State sized chuck of the chip), getting the ownership on their resume, finding a new non-Intel job, and splitting.
    So, every part of the chip got a new guy every 9-12 months who blamed everything on the previous owner, forced a re-design on the part (which may have been needed, but seemed to be needed an awful lot), and then left (forcing the cycle to repeat).

    3) Constant Re-Design
    Look I know re-design is part of engineering. But perpetual hamster-wheel-like re-design is not good. Nothing got finished!!!! No specification was stable (let alone the written specs; I mean verbal specs). You ask people (and this was years, years into the project) about your interface to their part of the chip and they wouldn't have coded it up yet. So, who knows what the Hell the timing issues would be. "Can I move a flip-flop to your unit?" "Go fish. I haven't coded that."
    Let us also remember that back then (I doubt they still do this) you coded in iHDL (not VHDL or Verilog) using macros for AND & OR gates. So, you're basically doing stencil EE work using a programming language. You want an IF-THEN construct, well break out the K-maps because you'll need them.

    4) Moral
    After the chip had slipped 2+years, no one wanted to work on this thing anymore. They had to freeze internal transfers. You had to threaten to quit to get out. "I am leaving Itanium. Are you going to make me leave Intel to do it?"

    • by Vellmont ( 569020 ) on Monday February 16, 2009 @09:55AM (#26871541) Homepage

      I worked on Itanium/Merced. Keep in mind I was mid-level (not high enough to see the good political fights first hand, only getting the after effects).

      I have to believe that there were forces inside Intel that wanted Itanium to fail. It's hard for me to believe that if the project was this important they wouldn't have pulled some Top Guy that Gets Things Done on the project.

      After the chip had slipped 2+years, no one wanted to work on this thing anymore.

      Back in 2000 or 2001 I went to JavaOne and went to a talk by some Intel engineers about how cool Itanium was going to be. They had to be he least enthused about any project I'd ever seen. The paper features sounded pretty cool, but you'd talk to them and you could just tell they thought the thing was a total piece of garbage. They didn't say it outright of course, but the sounds of their voices and the expressions on their faces told a very different story.

    • by dpilot ( 134227 ) on Monday February 16, 2009 @11:30AM (#26872613) Homepage Journal

      Outside perception - it started even before you say but really rooted in your reason #1.

      From what I could see IA64 wasn't really started for reasons of pushing technical performance, the problem being solved was the existence of clone designs. All of the IA64 IP was held by a third company, and then licensed back to Intel and HP. That way, none of the IP would be covered by existing Intel or HP cross-licensing agreements. Then the architecture had to be sufficiently different that it would be fully covered by that IP, and none of the essentials covered by anything else.

      So the initial design point was driven by legal and marketing concerns, and technical considerations were a distant third place, if that high.

      That's the impression from one well versed in chip design who watched from outside.

  • Why stop at flops ?
    Itanium easily qualifies itself as a mega-flop !

  • by JakiChan ( 141719 ) on Monday February 16, 2009 @05:56AM (#26870413)

    Itanium did one thing killed a lot of other chips. The threat of it killed MIPS post-R12K plans - and the Alpha, and PA-RISC architectures as well.

    I remember how SGI kept the team around that was going to work on their next-gen processor while they were negotiating with Intel. These guys had no work - they just played a lot of foosball in good old Building 40 (yeah, Google, you weren't nearly cool enough to build that campus). Then once SGI had sold it's soul they axed the project (and the team). That was a sad day...

    • by anss123 ( 985305 ) on Monday February 16, 2009 @06:14AM (#26870477)

      Itanium did one thing killed a lot of other chips. The threat of it killed MIPS post-R12K plans - and the Alpha, and PA-RISC architectures as well.

      Here's an idea: Let's throw out years of proven engineering in favor of an architecture that has yet hit silicon. That way we can fire our engineers and pocket the change. What could possibly go wrong?

      I feel a big bonus is coming up, and just to be safe let's add a parachute too.

      • Here's an idea: Let's throw out years of proven engineering in favor of an architecture that has yet hit silicon. That way we can fire our engineers and pocket the change. What could possibly go wrong?

        You must have been there...Belluzzobub, is that you?

      • Alpha was starting to hit clock speed limits, or at least, DEC wasn't able to increase them (shock amazement.) PA-RISC = garbage, at least compared to the modern competition. MIPS is still around as an embedded core - it wasn't keeping up with x86 either, which is why SGI tried to make x86 machines. All of these processors have basically no reason to exist whatsoever now that Hammer is around, with superior TDP and unparalleled ease of SMP. Then again, the same is true of iTanic :)

    • I was at SGI (mtn view) during that time, also. we called the intel chip and system 'IBT' (intel box thing) ;)

      it killed MIPS and was helping to kill IRIX, too (irix has little relevance outside of the mips cpu).

      it was truly the beginning of the end for SGI. I watched as SGI disappeared before my eyes. very sad.

      SGI was dying anyway but this chip really did put the nail on the coffin for SGI.

    • Google, you weren't nearly cool enough to build that campus

      little known fact: SGI was in its last days when it built the 'charleston buildings' (ones very close to the shoreline park). I was on the site I/S team that was doing the building planning, network planning and whole add/move/change team.

      what struck me as 'interesting' was that we designed those 3 floor buildings FOR US but intended *eventually* to be leased out to multiple different non-related companies. that makes designing your network infra.

    • y'know, i'm embarrassed to say i never made that connection before. that's a really interesting line of thought.
      still, MIPS was having lots of other problems, including a rather big split in focus between high-end servers and embedded systems, two markets with very different design constraints; schizophrenia probably did them in. that and getting in bed with WIntel.
      PA-RISC was a pretty obvious knock-off, but no sympathy for HP making their own stupid decisions. the most direct and disappointing casualty was
  • POWER and PowerPC? (Score:5, Insightful)

    by dlundh ( 158421 ) on Monday February 16, 2009 @06:06AM (#26870441) Homepage

    Why is that even in there? It "only" powers all three current games consoles and IBMs Power Systems server lines (i and p).

    If that's a failure, I hope IBM has many more failures in the future.

    • We probably have as many PowerPC chips in our homes than x86 these days. How many people own two of the following game consoles but only have 1 PC in their home? GameCube, Wii, xbox360, PS3?

      It's true that Apple killed PowerPC on the desktop and it will probably never come back. And ARM and Atom will fight over the mobile and netbook market.

      The article doesn't mention POWER, so I think we can technically assume it only considers PowerPC a failure (which is wrong of course). Even though POWER and PowerPC are

      • PowerPC is a massive failure on the desktop and everyone who invested in a PowerPC-based desktop computer got burned. End of story! I might add that it was a technical failure as a desktop processor as well. It was the most powerful thing going twice, for about fifteen seconds each time; with the G3 (which was NOT faster on all workloads) and the G5 (which was about the most expensive thing Apple ever kicked out the door.) Everyone stuck with a PPC mac right now has been enjoying a reduced level of support

      • by unfunk ( 804468 )
        Agreed. Wikipedia [] also points out that the PPC architecture has been the polar opposite of a "flop". No, it didn't take over the Desktop Computing world, but it sure made an impression just about everywhere else.
  • by thbb ( 200684 ) on Monday February 16, 2009 @06:06AM (#26870447) Homepage

    Commenters seem very young today. Noone remembers the failures of Intel's and Motorola first attemps at addressing RISC designs? Both the Motorola 88000 [] and the Intel i860 [] were great designs that failed.

    • i860 shows up on a LOT of hardware raid controller boards.

      hardly a failure of the chip or its design. worked great and didn't need huge heatsinks.

      its not a gen purpose cpu - so what's your point?

  • Transmeta (Score:2, Redundant)

    by tkrotchko ( 124118 )

    It probably won't be popular to say around here, but Transmeta was a fairly spectacular failure, particularly the Crusoe line.

    • I won't be popular, but it's still true. The whole idea of a cheap, low power, code morphing, software-upgradeable x86 CPU sounded great on paper... until actual benchmarks that it performed rather poorly, with marginal power consumption improvement.

      Another spectacular failure, IMHO, was the transputer [] - an amazing concept, specially for its time.

  • Did anybody else read that as A Brief History of Flip Flops?
  • MAJC missing? (Score:2, Interesting)

    by inkhorn ( 650877 )

    And what sort of thorough article would this be in missing out Sun Microsystems' MAJC chip from the 1990s ?

    Promised to accelerate JAVA instructions, the chip was a multithreading multicore design (can you say Niagara?) but Sun couldn't get it to market fast enough and advances in general purpose CPUs left it for dead.

    Sadly MAJC only made it into two models of Suns own-brand graphics cards before it was dropped, though it's design principles live on in Niagara and Rock.

  • Just because a chip isn't available in the PC at your local Best Buy does not make it a failure.

    From zSeries, iSeries, and pSeries, machines which make up a large number of server and midrange hardware sold to variations of the theme in some of today's popular gaming platforms I think the PowerPc as an architecture does just fine. G5 is alive.

  • by gnalre ( 323830 ) on Monday February 16, 2009 @08:43AM (#26871113)

    Intel's i960 was a nice chip for embedded development. One of its nicest features was the large number of individual interrupt vectors which is really useful when you want to hang off a large number of I/O devices off it. Compare that to the x86 where they have to share interrupt vectors. For some reason however Intel decided to drop the whole line and move to ARM architecture instead.

    However the second one is a what might of been. During the 80's we did a lot of development using INMOS T2 and T8 transputers. They were a joy to use and made parallel programming at software and hardware level so easy and natural. The next iteration was to be the T9000. It promised a lot, much improved execution speed, a faster and more flexible processor interconnects. It looked so good we had even sold our next project based on it. However when we started getting the first samples there was obviously something wrong. Bits of the chip did not work or would fail. At the end of the day it looked like INMOS just could not deliver. The T9000 never became a reality but anyone who used transputers how good they were and and could if it had been done right with enough finance could of fundamentally changed the computer industry.

  • by argent ( 18001 ) <peter&slashdot,2006,taronga,com> on Monday February 16, 2009 @09:07AM (#26871241) Homepage Journal

    ... to be precise, by intel's bankroll and investment in process.

    Power PC and Alpha were outcompeted by the fundamentally inferior x86 family not because of flaws in their designs, but because intel spent more on improving their process than anyone else.

    Both the Power PC and Pentium turned into furnaces, the Pentium 4 and G5 were both following the "megahertz myth" into long pipelines to let the clock speed ramp up. Neither got the clock speeds they were hoping for. Both were too hot for mobile processors. In both cases the solution was going to be shorter pipelines, slower but more clock-efficient cores, and faster busses. The Freescale e700 was torpedoed when Apple went with Intel's Core Duo... because Intel had the resources to get their respin of the PIII out quicker than Freescale could get their respin of the G4 online.

    So now we're still using hacks upon hack on the truly horrible x86 architecture.

    Well, it could have been worse. It could have been SPARC.

    • Re: (Score:3, Insightful)

      Well, it could have been worse. It could have been SPARC.
      What's wrong with SPARC? I took SPARC assembler and x86 assembler during the same semester my first time through college (i.e., before I dropped out), and it made the x86 class pretty unpleasant. SPARC actually left you the impression that somebody put some thought into it before they started making them.

No problem is so large it can't be fit in somewhere.