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Hardware Software Linux

Tilera Releases 64-Way Chip Dev Tools 72

eldavojohn writes to tell us that Tilera has released a Linux-based development kit for their 64-core system on a chip. "The Tile64 is based on a proprietary VLIW (very long instruction word) architecture, on which a MIPS-like RISC architecture is implemented in microcode. A hypervisor enables each core to run its own instance of Linux, or alternatively the whole chip can run Tilera's 64-way SMP (symmetrical multiprocessing) Linux implementation. An 'iMesh' switching interconnect, developed by Tilera's founder, MIT professor and serial entrepreneur Dr. Anant Agarwal, is said to eliminate the centralized bus intersection that limited scalability in previous multicore designs."
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Tilera Releases 64-Way Chip Dev Tools

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  • I used the 64 way chip to get first post!
    Which of the 64 ways did you use? And did you have fish with the chips?
  • CISC? (Score:1, Informative)

    by friedman101 ( 618627 )
    I'm not sure about this particular chip but doesn't VLIW normally mean no microcode? Microcode is the set of RISC commands that make up a CISC command. VLIW is just a RISC machine in which the compiler does all the optimization (branch prediction, hazard detection, etc). Normally VLIW machines fetch multiple instructions at once and issue them without fear of any hazards because the compiler takes care of it. Very neat idea, but not CISC
    • CIISC and RISC describe the architecture. Either can be implemented directly, using horizontal or vertical microcode, or via a translator. RISC is similar to vertical microcode, where each micro-instruction controls part of the core, and VLIW is similar to horizontal microcode, where each micro-instruction controls a number of components at once. Whether you call them "microcode" or "RISC/VLIW" is almost more a matter of marketing at this level, like when Intel started talking about the 486 having a "RISC c
    • No. All processors have microcode, including the most infamous VLIW chip the Itanic. You're confusing yourself.
      • All processors have microcode? Is this true? I thought some were pretty mechanistic little devices (moreso in history.) Today, of course, everything is pretty complex and there is almost nothing purely RISC or CISC (not sure about VLIW-land.)
        • Actually you're probably correct. I should have said "all modern general purpose CPU's." My point was that VLIW style chips still use microcode. Different things.
  • Oblig. (Score:3, Funny)

    by r_jensen11 ( 598210 ) on Wednesday April 30, 2008 @11:22PM (#23259894)
    Imagine a beow... oh, never mind....
    • by jd ( 1658 )
      Actually you might want to imagine a Beowulf cluster of them. You'd more likely run MOSIX or OpenMOSIX on the chip to handle the migration from logical machine to logical machine on the same chip, but you can't then use that to build a cluster as you'd get a conflict between the cluster and cluster-of-clusters. SMP and virtualization might work, but there's minimal messaging between nodes and SMP technology doesn't scale well beyond 16 nodes, so a clustering technology seems a more logical way to go.
  • I thought the chip has been out for a few months; I feel bad for anyone who has been trying to use the processor with no development tools.

    Also, it looks like the tools have been released to Tilera's customers, not to the public. A shame, since I'm sure a lot of Slashdotters would like to at least gawk at the docs for this chip.
  • by rossz ( 67331 )
    I hate press releases like this. "$435 in 10,000 quantities". How much for just one of the damn things with the software I need to fool around with it? Is that too much to ask? It would be cool to have one of these, but I'm sure it won't be worth the effort or the expense (I figure a single unit will be at least double the quantity price).
    • Wouldnt you be looking for a development board for it?
    • by quarrel ( 194077 )
      I hear what you're saying - it is sort of annoying.

      However, a VC funded startup like this has to be focused. They're going to have a list of customers probably about 10 companies long that they want to sell to, and everyone else at this stage is a distraction. Your $1000 does nothing for them, you and your 2000 friends barely helps.

      They're going to want Cisco, Juniper, Nortel, Lucent-Alcatel, 3Com, Huaweii, maybe 1 or 2 of the big telcos and that's about it (ok, there are a couple of other big-iron vendors,
    • This may be a stupid question, but what does $435 in 10,000 quantities even mean?
      I either get 10,000 of them for $435 (working out to about 4 cents each) or they cost $435 each with a minimum buy of 10,000 (total spend: $4,350,000). These seem incredibly cheap and incredibly expensive respectively. Am I interpreting it wrong?
      • they cost $435 each with a minimum buy of 10,000 (total spend: $4,350,000).
        that one
      • by jandrese ( 485 )
        $435 each, and that's not horribly expensive when you consider where they're coming from. In fact for a first gen device like this from a startup it's downright inexpensive.
  • I went on to read their in-depth article (linked to the main article) at [] and I found this:

    "Another touted benefit is the ability to consolidate control- and data-plane functions on a single device, with "solid-wall" processor boundaries reinforcing security and licensing containment barrier. In this regard, the Tile64 chip resembles another heavily multicore MIPS64 chip, Cavium's 16-way Octeon."

    Does anyone know what the heck a "licensing containment barrier" is
    • by quarrel ( 194077 ) on Thursday May 01, 2008 @12:16AM (#23260136)
      > It definitely sounds like a performance hit if it's turned on.

      No, if anything they pitch it as a performance gain.

      The idea is to run Linux (or OS of your choice), with various control plane functions (it can have an IP address, you can do config, stats collection etc etc), on say (making up these numbers!) 4 of the cores, while the other 60 cores are running without an OS (they offer a BIOS like environment with basic functions to get access to the backplane and subsequently the packets) doing data-plane functions, perhaps doing deep-packet inspection for QoS delivery, security functions (IPS?) etc.

      The Linux side, particularly the kernel isn't going to contain your real IP, while the data-plane side is all your secret-sauce. It involves embedded style programming without lots of OS support, but you get speed and the networking vendors are used to this sort of model - it sure beats the hell outa doing it in an ASIC on the dataplane side which is what they're used to.

      This isn't an attack on open source - it's using it in a sensible fashion IMO. However, for the paranoid types who've seen the fud, they probably pitch this split of operations as a "licensing containment barrier" cause a marketing person thought it might help somewhere.

    • by jd ( 1658 )
      It's like an antimatter containment field - circular and serves the purpose of being dramatic on television.
  • Can anyone please translate this to Layman? I mean I do know bits and pieces about computing but this is really unintelligible for anyone but maybe hardware engineers.
    • Dunno-I think it'd be more coherent if I hadn't flaked on my organization & architecture class (where we used MIPS), but still-eek.

      The idiots version: (with help from wiki) This chip carries out one instruction [] that's really filled with tons of different instructions-(basically whatever can fit in 48 bits-and because it's treated as one instruction-instantish parallism) and does so using assembly code similar to MIPS assembly. Then it offers two options for a core running it's own instance of linux- v []

    • Simple version. (Score:5, Informative)

      by jd ( 1658 ) <imipak@yaho[ ]om ['o.c' in gap]> on Thursday May 01, 2008 @02:20AM (#23260628) Homepage Journal
      They have set up an 8x8 grid of processors, not unlike a chessboard. Each square on this grid can talk only to adjacent squares (up, down, left, right), with the edge squares connecting to I/O devices. They refer to their network as a mesh, but the correct term for this design is a Manhattan Network. This is not significantly different from a processor I dearly loved in the late 80s, the Transputer. That, too, had 4 connections from each processor, but you were not restricted in how you connected the Transputers together. A grid, it transpired, was not efficient, you needed to arrange the connections to form a hypercube. (Yes, it's 2D, so it's actually a 2D representation of a hypercube. Now stop fussing or I won't get you that Beowulf cluster for Christmas.)

      I like the idea, I like the idea a lot, but the fact that they opted for a simple but slow topology doesn't fill me with hope. Especially as they suggest running SMP over it. Processors close to the centre of the "mesh" will be resource-starved. There needs to be strong affinity of a given thread to a given core, where the weighting is by the operations expected and where that weighting can (and will) shift as code blocks change or new threads start. In other words, you want something that is semi-static, semi-dynamic according to need. Only the OS is capable of obtaining that kind of information, so it is the OS that needs to do the dividing, NOT the architecture underneath OR a system administrator.

      • Re: (Score:2, Informative)

        by Anonymous Coward

        I like the idea, I like the idea a lot, but the fact that they opted for a simple but slow topology doesn't fill me with hope.

        hypercubes were great in the 80's when everything was multiprocessors and wire lengths didn't kill you. But it turns out that low-dimension networks (ie, a 2d grid) are faster for a network of cores fabbed onto a single processor. while you can decrease the number of jumps with hypercubes, you increase the amount of wiring (and the length of wires) that goes on the chip when you had more dimensions to your network. There are more variables that go into designing a network than just the number of hops a

      • Very lucid description. The other problem with the design is that you don't get what you expect; using a simple 4-way grid should give predictable latency costs between nodes. Unfortunately their routing algorithm is non-predictable so you can't statically schedule threads at compile-time to feed each other, it all has to use dynamic control-flow. Shame really.

        If you liked the transputer then you should look at its other descendant [] that is in the process of coming to market. There isn't a wealth of public i
      • I like the idea, I like the idea a lot, but the fact that they opted for a simple but slow topology doesn't fill me with hope. Especially as they suggest running SMP over it. Processors close to the centre of the "mesh" will be resource-starved.

        These chips seem to be designed for specific applications, not as a general purpose CPU, especially in the DSP and digital video markets. I found this [] and this [] .

        I don't see these chips as being that revolutionary or anything. Yes, they are similar to the transput
  • The press release, oh pardon me, the article linked to in the posting above lists pricing in units of 10,000. I want one or two TILexpress-64 boards please, not 10,000 units. Until the software is built 10,000 units would just sit in my garage doing nothing.

    Also, I guess they had to put out a press release to respond to the massive threat that NVidia's new Tesla board represents. At least this is going to be good for competition.
  • [] , just in case someone hasn't dug on these yet (my personal fave).
  • VLIW (Score:3, Funny)

    by ravrazor ( 69324 ) on Thursday May 01, 2008 @10:11AM (#23263554)
    Okay, so I know that VLIW stands for some very long word, but couldn't you have told us what it's an acronym for anyway?
  • sounds impressive =) "Tilera claims that the Tile64 outperforms Intel's dual-core Xeon processor by a factor of 10, while offering 30 times better performance per Watt." and "The Tile64 is available now, in three variants differentiated by I/O mix and clock. Pricing starts at $435 in 10,000 quantities".
    where can i buy this?

If I'd known computer science was going to be like this, I'd never have given up being a rock 'n' roll star. -- G. Hirst