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Low Voltage Is Key To Energy-Efficient Chip 127

An anonymous reader writes in with news from the International Solid State Circuits Conference in San Francisco of a new energy-efficient chip designed by researchers at MIT. It's said to be able to run on 1/10 the power of current chips. Texas Instruments worked with MIT on the design, which is maybe five years from production. "The key to the chip's improved energy efficiency lies in making it work at a reduced voltage level, according to... a member of the chip design project team. Most of the mobile processors today operate at about 1 volt. The requirement for MIT's new design, however, drops to 0.3 volts."
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Low Voltage Is Key To Energy-Efficient Chip

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  • by WiglyWorm ( 1139035 ) on Tuesday February 05, 2008 @07:18PM (#22314494) Homepage
    But how well does it overclock?

    • You can run one of these puppies for a week on a AA battery.
      • by Anonymous Coward

        don't fuck with the boys from MIT

        they can kick your ass using nothing but their brain waves from their slightly downturned head and funneled through their fingertips

        laughing now, who is

    • But how well does it blend?
      There, fixed that for you.
    • Why do overclockers have to ruin everything? Who gives a crap? Buy the chip and save some money from low power usage. It's obviously not engineered for overclocking so go out and rice out a Civic instead because it's the same damn thing. And yes. I just made a car analogy. There ya go.
  • WHAT 9000
  • noshitposter (Score:1, Insightful)

    by Anonymous Coward
    I see someone tagged this "noshitsherlock". But this is a hard thing to do because the difference between "0" and "0.3" is smaller than "5" lowering the immunity to upsets like noise.
  • by EmbeddedJanitor ( 597831 ) on Tuesday February 05, 2008 @07:22PM (#22314536)
    Less transistors switching per unit of work done means better power performance.

    That's why your cell phone has an ARM CPU and not an x86.

    • From what I gathered in the article, thats just what they did. Namely change the architecture of the memory cells so they could lower the voltage without loosing volatile memory to noise. I think it said they moved from 6 transistors per cell to 8 though I'm not clear on how the arrangement changed. Simple J/K latch or S/R latch changed how exactly? I guess it has been too long since digital logic.
      • by unitron ( 5733 )

        I guess it has been too long since digital logic.

        Or for some of us who suffered through it, not nearly long enough :-)

      • Your typical SRAM memory cell uses a simple double inverter loop, plus transistors to switch the rows. To change the bit, you effectively short out the inverters using higher power transistors. This saves chip area but wastes power. I guess they moved to a design that doesn't depend on this "brute force" method and instead gracefully changes the state of the cell using logic.
      • A 6T SRAM cell consists of two cross-coupled inverters, and an access NMOS transistor on each side to connect the state nodes to bitlines. Writing is done by charging one bitline, and discharging the other. The devices should be sized such that the drive strengths allow the values on the bitlines to overwrite the values on the state nodes (i.e. win the drive fight). When you do a read, both bitlines are precharged, then the state nodes are connected to the bitlines by turning on the access transistors.

    • by johnhennessy ( 94737 ) on Tuesday February 05, 2008 @07:53PM (#22314896)
      Less transistors switching is only part of the story.

      Maybe a more signficant factor in determining the power consumption of a CPU is the technology process choice.

      Intel typically tune their process for performance, at the expense of leakage. This lets them squeeze out a couple of GHz in terms of clock speed, but it means that the power consumed when the chip is doing nothing at all (i.e. idling) is much larger. The CPUs that are put into cell phones (from companies like ST, TI, Broadcom, etc, etc) are normally fabbed with a "low power" or LP option. This reduces the maximum speed that you can get out of the processor, but reduces the leakage problem significantly. If the cell phone is only using the processor 1% of the time (think of how long it spends powered on in your pocket), then there is no point in having the best 3D games on your phone, if the stand-by time is 15 minutes.

      Switching between these standard (or GP) processes and LP processes is not quiet straight forward, as you need to design all your mixed-signal / analog blocks (think PLLs, bandgaps, regulators, etc) for both nodes. While I'm sure Intel could probably afford to do this, they would then have to turn around and support this process in their fabs, which would eat up their resources for their processor market.

      If you compare the numbers: Intel can sell their processors for hundreds of dollars. Phone manufacturers buy processors from the other Semicos at about 10-15 dollars each. Guess where the better margin is ...
      • by imgod2u ( 812837 )
        One of the primary techniques introduced with the Banias line of processors was multi-VT cells. Since then all of the other major foundries have adopted this as well. Off the top of my head, IBM and TSMC both provide this. The high-VT cells use high threshold FET's that switch slowly but leak little. The low-VT cells leak a lot but switch very fast. You then choose, based on your design and timing margin for each circuit path, what cells to use. This cuts down power a lot if you have a lot of really f

        • The Vt of the standard cells is not the same as the process option. You can get a "Low Power" process with low and high Vt cells, and likewise a "High Performance" process with lowand high Vt cells.

          See the bottom graph on: []

          The "Core Devices" contain the standard cells. UMC call "SP" the normal leakage process, and "LL" the low-leakage process. TSMC have similar.

    • by imgod2u ( 812837 )
      This is becoming less and less true. Leakage power is a dominant if not *the* dominant factor nowadays. So even transistors that are idle will draw a significant amount of power. The problem becomes worse as transistors get smaller. The idea nowadays is not only to dynamically clock only circuits that are active (thus reducing unnecessary switching activity) but to scale and shut off the voltage supply when a transistor is not active. The MIT guy's website contains a previous design for a fast-tracking
    • No. Power increases linearly with the number of transistors switching. Power increases with the square of the voltage supplied to those transistors.
  • by pezpunk ( 205653 ) on Tuesday February 05, 2008 @07:25PM (#22314566) Homepage
    aparently from the Bureau of Slowly and Painfully Working Out The Obivous.
    • aparently from the Bureau of Slowly and Painfully Working Out The Obivous.
      Either that or John Madden [] is writing headlines for Slashdot. Can he really top this gem?

      "Hey, the offensive linemen are the biggest guys on the field, they're bigger than everybody else, and that's what makes them the biggest guys on the field." - John Madden
      And, as it turns out, yes you can. The key to being energy efficient is using less energy!
      • And, as it turns out, yes you can. The key to being energy efficient is using less energy!

        So if I leave Chicago heading eastbound at 9 PM and drive 5 miles at 7000 rpm in my convertible... and you leave NY at 10:30 PM and drive westound for 50 miles at 2000 rpms in your Canyonero... who has used less energy? But importantly, who was more energy efficient*?

        And most importantly, and what time does train A jump the tracks and decapitate me for bringing a car analogy to a football analogy fight?

        *[hint] it

    • Power = Current * Voltage

      To reduce power consumption, you either have to reduce the voltage or the current.

      If you shuffle your feet across the carpet, you'll generate static electricity at thousands of volts. The reason that this doesn't kill you is that the currents are absolutely tiny, making the power transmitted between your socks and the carpet also extremely small, and non-hazardous.

      These guys are claiming that we can most effectively reduce power consumption by focusing on reducing the voltage requi
      • by Pulzar ( 81031 ) on Tuesday February 05, 2008 @10:09PM (#22316296)
        Power = Current * Voltage
        To reduce power consumption, you either have to reduce the voltage or the current.

        While your formula is right, it's not too applicable for chip power usage because current is not a constant. The formula you will normally see is

        P = P-switching + P-leakage

        Now, P-switching = fCV^2, so you can reduce it by reducing the clock frequency, voltage, or the number of transistors. But, P-leakage actually increases exponentially as the gate threshold voltage is reduced -- so, reducing the voltage too much will not help, either. There's only so far you can go before leakage power becomes the dominant one and reducing voltage further doesn't help.
        • by imgod2u ( 812837 )
          I think you're confusing threshold voltage with supply voltage. A transistor with a lower threshold voltage will leak more. That's an inherent property of the transistor depending on its dimensions and the process.

          The supply voltage (which is what's being scaled) is what's put onto the end of the MOSFET's that is attached to the source. The lower this voltage, the less leakage there will be. If this voltage is 0.0001V, there will be virtually no leakage as the transistor is pretty much powered down.
      • by v1 ( 525388 )
        This article seems counter intuitive. Power lines in the US are higher voltage, lower current, than local transmission lines, to reduce power loss on their primary feeds. Higher voltage means lower current, for the same power transmitted. Isn't it current passing through a resistance what causes power loss? So lowering current (and in turn raising voltage, so the power transmitted remains the same) the proper way to reduce power loss via transmission? Or am I missing something?
        • Re: (Score:2, Informative)

          by Malekin ( 1079147 )
          You are correct about power lines. The high voltage / low current reduces power lost due to the resistance of the wires. When you're dealing with long pieces of wire, the resistance adds up. Integrated circuits, however, are very small and though they are made of semiconductors (which are generally more resistive than metals) resistive losses aren't the big concern. In a semiconductor the important things are electric fields and charges moving about. Making a transistor work at low voltage means there a
    • Contrary to popular belief, voltage is *not* power. To use the analogy properly, what this article says is closer to "low horsepower key to better gas mileage". Which, while still obvious, is at least not a tautology.

      It is possible for a low voltage system to transfer more energy than a high voltage one in the same amount of time if the low voltage one transfers more current (current is measured in amps, not volts). The exact relation is volts * amps = power (in watts). So if this chip ran at lower volt
  • I don't get it. As far as I know, transistor Vbe is still around 0.7V. How do they build circuits when the supply voltage is less than that? I mean, how can you fit in resistors and stuff when you have no room to drop anything?
    • Re: (Score:3, Informative)

      by AuMatar ( 183847 )
      You don't use resistors in CMOS logic. You take a transistor and wire source to gate. This turns it into a constant load, more or less the equivalent of a resistor of 10-100K ohms.

      The activation voltage of a transistor is variable- it's a property of the materials its made of. .7 is a common one and thus used in a lot of texts, but it isn't set in stone.
      • by austexmonkey ( 1108037 ) on Wednesday February 06, 2008 @12:23AM (#22317216)

        Dear God, how did this get modded Informative? The parent is confusing CMOS logic with NMOS logic (you do NOT use static loads with CMOS logic), and FETs do not have a parameter called "activation voltage".

        For a description of CMOS logic that's actually accurate, check out the wikipedia article here: []
      • by unitron ( 5733 )

        The activation voltage of a transistor is variable- it's a property of the materials its made of. .7 is a common one and thus used in a lot of texts, but it isn't set in stone.

        --unintentional pun alert--If you count silcon as a stone then actually it is. It takes between 0.6 and 0.7 volts to get a silicon PN junction to conduct, but that's Bipolar Junction Transistors, and Field-Effect Transistors are a different situation where you don't want the junctions to conduct.

        • by imgod2u ( 812837 )
          I don't think that's true. The P-N-P junctions still conduct in a FET. It's just that the control mechanism is a gate insulated with a dielectric. The control (base in BJT language) then does not need to actually supply current (unlike a BJT) to cause the channel (N channel in the case of PNP) to become conductive. The electric field produced by the gate-to-drain (Vgd) terminals (which have no current flowing through it) will cause the channel-to-drain junction to break down and conduct.

          An abstract way
      • Re: (Score:3, Interesting)

        by Komi ( 89040 )
        The activation voltage of a transistor is variable- it's a property of the materials its made of. .7 is a common one and thus used in a lot of texts, but it isn't set in stone.

        It's also a property of the doping levels of the silicon. Basically, you need to bring a certain amount of charge under the channel to turn the device on. This depends on the substrate material, but also depends on how much charge is available (i.e. doping).

        In a given process, you can different flavors of transistors, each with it

    • Well you only need to exceed Vbe (and the concept of Vbe only exists) if you have bipolar switching transistors. They're using IGFETs of some kind. I'm guessing that the way they do this is by making the channel and the gate insulation really thin, so you only need a tiny electrical field to switch it. I bet the noise immunity and rejection of external electrical and/or magnetic fields is really poor.
    • by jhines ( 82154 ) <> on Tuesday February 05, 2008 @07:35PM (#22314704) Homepage
      In Germanium the voltage is 0.3, if I remember correctly. So it depends on the materials used.
      • You do not remember correctly. Saying "Germanium voltage is 0.3" is like saying "Ford cars are red." Note that regular silicon devices can operate as low as 0.3V up to 40V and beyond. The material used does not dictate the voltage; the process and structure design do. I.e. Here's [] an SiGe chip that uses 5V power.
    • by Durinia ( 72612 ) on Tuesday February 05, 2008 @07:37PM (#22314726)
      In this case, they're operating the transistors in a sub-threshold voltage environment. A full channel never opens for the transistor, but energy will trickle through at different rates.

      Instead of the typical "open/closed water pipe valve" model of the transistor, imagine having a leaky bucket, and then determining 1 vs 0 on how many drops get through.

      It's a tough area to design circuits in because of the very delicate balance. It doesn't take many electrons (or much process variation) to bust up your circuit.
  • Physics (Score:1, Interesting)

    by Anonymous Coward
    Hmm. P=V^2/R, so dropping the voltage from 1 to 0.3 drops the power by a factor of (1/0.3)^2 ~ 10. How many MIT researchers did that take?
    • I'd say it took quite a few to figure out how to make it work at 0.3V.
    • The electrical characteristics of a CPU are somewhat more complicated than those of a resistor.
      • Re:Physics (Score:5, Insightful)

        by Chris Burke ( 6130 ) on Tuesday February 05, 2008 @08:19PM (#22315260) Homepage

        The electrical characteristics of a CPU are somewhat more complicated than those of a resistor.
        True, but in fact a chip's power does scale with the square of the voltage. At a gross level you can approximate the chip as a certain constant resistance for static power, aka leakage, and as an RC circuit with a given constant for dynamic power, which scales linearly with frequency as well. Nobody actually does that, they just measure the power consumption and know that they the number is proportional to voltage squared and frequency.

        Of course I just knew some jackass was going to use this fact to try to downplay the achievement. Okay, yeah, every computer engineer knows that to reduce power by four you drop the voltage by half, but the trick is actually making this work. That's why not every chip runs on 1E-20 Volts, Mr. Anonymous Idiot.
        • That's why not every chip runs on 1E-20 Volts, Mr. Anonymous Idiot.

          At subthreshold, power draw from leakage current begins to become more important than transient switching power and the V^2 factor no longer dominates. Then further dropping the voltage increases the energy used to accomplish tasks.

          • Re: (Score:3, Informative)

            by Falstius ( 963333 )
            self correction/clarification: in subthreshold leakage current beings to become more important, eventually you stop gaining from dropping the voltage. That can be well into subthreshold, I've seen chips which run at 0.2V (a 45nm process has a threshold on the order of 0.5V). I didn't mean to imply that any drop into subthreshold was self defeating.
          • Oh I thought the leakage power component still could be approximated as a resistive circuit, but like I know anything about sub-threshold circuits. What's the scaling factor?
            • Its complicated .. in short, power is always equal to voltage times current. In deep subthreshold, the transistors don't turn off very well and so there is more leakage current. This relative current goes up exponentially as the voltage drops, where as the voltage is dropping linearly, so the energy lost to leakage does not drop as fast. The active power (power used to switch transistors) does continue to drop, but the gate delay increases. At some point, dependent on the process, the two curves cross a
        • Power tends to be proportional to fCV^2, yes. But the achievable clock frequency f is actualy a function of V. Higher voltages = lower gate delay = higher freq, as many overclockers have discovered. So power tends to scale with V^3. (Assuming you are getting the optimal performance out of your process technology. I mean you could increase V and not take advantage of the bonus in f and only use ~V^2 more power, or decrease f wihtout decreasing V to use ~V less power, but that would mean you were wasting
  • Will this reduction in voltage and increase in energy efficiency reduce the amount of heat generated by the chip? It would be nice to have a powerful laptop that I could actually use in my lap (without fear of roasting my dangly bits).
    • Power is equal to the voltage multiplied by the current, so if the current stays the same and the voltage drops to 1/3, well, so does the power.

      (Yes, I'm well aware that's only ohmic power, so shoot me.)
    • by amorsen ( 7485 )

      Will this reduction in voltage and increase in energy efficiency reduce the amount of heat generated by the chip?
      In this house, we obey the laws of thermodynamics!
  • Great!

    I'm waiting for several years now for a system that is completely silent, uses very low power and does not heat my room. And can be used and accessed all the time. And of course, one that does not make the performance penalties that VIA makes in their current EPIA offerengs (otherwise I would be there).

    Fortunately this seem to be going to happen in the very near future. Chipsets and CPU's are partially powering down where ever possible, and with a flash SSD's there is no spin-up or (loud) rattling whe
    • Re: (Score:3, Informative)

      by tknd ( 979052 )
      With the latest hardware and fully integrated chipsets, you can already build an incredibly power efficient system for as low as 20watts idle, and yes, it will perform better than the VIA platforms. Here's one example. []
  • I guess they just figured out what the industry has known for years. Doesn't anyone notice that voltage requirements have been going down as power goes down?
  • Wow! (Score:4, Funny)

    by StaticEngine ( 135635 ) on Tuesday February 05, 2008 @07:50PM (#22314860) Homepage
    If they can just get this thing down to zero volts, this chip will run forever!
    • Re: (Score:3, Funny)

      by ChrisMP1 ( 1130781 )
      0V processor []
    • Re: (Score:3, Funny)

      by ichigo 2.0 ( 900288 )
      Nevermind that, they need to get it down to negative voltages, then all our energy problems would be solved!
      • Power increases with the square of the voltage. (-x) is a positive number. You can already make CPUs that run on negative voltages: just swap all of the transistors (roughly). Or you could just take a normal CPU and rewrite the specs to put the 0 at the positive rail, call it ground, and mention that the chip uses inverted logic I/O. Voila, a negative voltage CPU.
      • by thegnu ( 557446 )
        Computer, 9.
        3 + 6

        Computer, 2.54.
        How many centimenters in an inch?

        Computer, 42.
        6 x 9
    • Just make a dual core CPU, and have one core run on +5 volts, and the other on -5.

    • Re: (Score:2, Interesting)

      by Spy Hunter ( 317220 )
      Actually, I seem to recall reading about a guy who had proven that there was no theoretical lower bound on the amount of energy it would take to do a given computation (assuming the computation was 'reversible' []). Contrast this to an electric motor, where the desired result is mechanical power output, so obviously at least as much electrical energy must go in as mechanical energy comes out. When the desired output is merely 'computation', there may be no lower bound on the energy input required.
    • Something that would help, is my NISC architecture. The Null Instruction Set Computer architecture. Not only does this architecture facilitate the lowering of the chip's voltage, you can also lower (or raise) the clock speed arbitrarily. The processor's clock speed can even be set to zero for the ultimate in power saving!

      (In addition, you can increase the number of dies on a wafer, practically arbitrarily!)

      I started developing the NISC architecture as an undergrad. I originally envisioned a NISC archite
  • Process Counts (Score:3, Interesting)

    by Colourspace ( 563895 ) on Tuesday February 05, 2008 @07:59PM (#22314986)
    It's very simplistic to say that with voltage drops comes power efficiency - process geometry and materials play a part here too (and I'm not even going to mention the issues with noise tolerance and problems with SSO - Simultaneous Switching Outputs at the 0.3v level). So called 'current' (90nm) geoms are a nightmare for power leakage due to the the relatively small atom thickness that goes to make the gate of the switching transistors. You need to look at such tricks as gate oxides and other power mitigating technologies... BTW - When I say 90nm is current, I know people are doing 65nm, 45nm, 32nm and beyond (which are, given process geometry/power efficiency/newer techniques slightly better in some ways) but the lower geoms are slightly ahead of the curve somewhat..
    • Re: (Score:3, Insightful)

      by randyest ( 589159 )
      The core voltage and the I/O voltage (which is where SSO is a concern) need not be the same, and rarely are in advanced processes. I'm sure the I/O's are not 0.3V. The rest of your comment was similarly confusing: using gate oxides aren't a "trick" (they're pretty much a requirement,) 65nm and under are more than "slightly" better then 90nm "in some ways," and I don't know what curve you're talking about.
      • Good points. I would still stand by the fact that even though what I said is slightly erroneous, most people on /. appear to be software rather than hardware oriented (not a bad thing just what I have observed)... And expect lower geometries to produce better results with little change to the technology underlying shrinks. I stand corrected though.. I do realise about the IO not matching the core voltage a little too eager to make my point. Not sure what I meant about curve right now but doesn't mean the po
        • As a hardware type here on slashdot I have to say that I think you may be underestimating our numbers. I should also say that lower (smaller) geometry processes do produce better results -- otherwise we wouldn't use them. No one is willing to pay extra just to print "45nm" on the package (does anyone even do that?) -- they pay for the increased performance, lower power, smaller die/package size, etc. I don't know what "with little change to the technology underlying shrinks" means, so I can't comment on
  • subthreshold circuits with dynamic voltage scaling are fun and stuff, but the real issue at small geometries is leakage currents which constitute the majority of power consumption. Traditional dynamic voltage scaling doesn't help much because leakage is dominated by the threshold voltage not the power rail. multi-threshold CMOS uses enable signals to turn on and off high leakage paths. this does not help with active mode leakage when the system does not need to operate at full speed. to reduce active mod
  • There have been 150-200mV microcontrollers (pdf) at the University of Michigan for some time now: [] Conference paper 3: [] what is new is TI and MIT are involved in a commercial low voltage product. But thats still 5 years out. MIT is good at getting press.
  • Power consumption (Score:5, Informative)

    by AdamHaun ( 43173 ) on Tuesday February 05, 2008 @08:30PM (#22315400) Journal
    Power consumption in a digital circuit can be approximated by the formula:

    Pavg = N*f*C*Vdd^2 + Pleak

    where N is the probability of a gate switching during one clock cycle, f is the clock frequency, C is the average gate capacitance, Vdd is the supply voltage, and Pleak is the power loss due to current leakage. Since power is proportional to the square of the voltage but directly proportional to everything else, reducing the voltage has a much greater impact on total power consumption. Going from 1V to 0.3V implies a >10x dynamic power reduction.

    • Further, from what I've read, leakage power is proportional to Vds. Assuming you use a balanced design in your process, That would mean the leakage current falls in respect to Vdd. So voltage has even greater an impact.

      Still, there's nothing quite as effective at reducing power consumption as reducing C with a process shrink. This kind of thing (sub-threshold operation) is only getting major news coverage now because we're hitting the limits on both voltage AND process technology.
  • The more voltage the more power, old computers and logic used 5V, 0.3V will be very hard to use because noise in the computer and in chips may reach 0.15 Volts, the absolute minimum resolution for the circuitry to distinguish between high and low voltage at 0.3 volts.
  • Researchers have proved that the secret to longevity is to continue to live without dying.
  • by CTho9305 ( 264265 ) on Tuesday February 05, 2008 @09:05PM (#22315808) Homepage
    TFA isn't very techincal, and makes it sound like the MIT team isn't doing anything very interesting (they mention 8-transistor SRAM cells, but even regular CPUs sometimes have to use them). The interesting story here is that the chip is being operated at a voltage below the voltage where the transistors are normally viewed as being "on". In this region, transistors operate more like amplifiers than digital switches.

    One cool thing about this is that the leakage power will be negligible. Leakage currents are generally exponential with respect to voltage.

    Another cool thing is that the chip can actually operate at the low voltage. It's not too hard to make a chip retain state at very low voltages, but as soon as you want to do anything you usually have to raise the voltage back up before execution resumes. Any task that requires a small amount of work frequently will benefit from something like this. A contrived example of where this make a big difference is in a poorly-architected MP3 player in which the CPU has to shuffle a few thousand bytes per second to a sound chip, but in very small chunks (this poorly-architected sound chip has a very tiny buffer), hundreds of times per second. A normal chip would be constantly jumping to a high voltage and going back to sleep; depending on how long the voltage transition takes, it might have to stay in a higher voltage state constantly. This chip, on the other hand, could operate continuously at the "sleeping" voltage.

    The catch is that transistors operating in the subthreshold regime are going to be pretty slow, so for any tasks that require high performance you'll have to bump the voltage back to a more normal range.
    • "One cool thing about this is that the leakage power will be negligible. Leakage currents are generally exponential with respect to voltage." leakage is more dependent on threshold voltage than Vds. running a chip subthreshold means you are relying on leakage to charge up capacitance. we've had this research going on for years at MIT.
      • by imgod2u ( 812837 )
        For a typical CMOS digital circuit, Vds will also be Vgs as far as I'm aware. So lowering supply voltage will decrease leakage.
  • (if you don't know, Silverthorne is intel's next-gen low-power chip for ultra-mobile applications)
    The article states it goes down to 0.3V at idle - so it doesn't actually _run_ at that voltage (just preserve register contents). Compare this to Silverthorne which has a C6 Deep Power Down State - coincidentally at 0.3V... The article also states that this cpu uses 8-bit sram cells instead of the usual 6-bit sram cells - Silverthorne also uses 8-bit sram cells for its caches.
    Granted maybe this design works a
  • Leakage Power! (Score:2, Interesting)

    by borowcm ( 1233996 )
    From what I can remember from my Low Power VLSI class...

    1. Dropping Vdd to a CMOS transistors requires you to drop the threshold voltage to maintain performance.
    2. As the two voltages approach each other, theres an increase in the current in the substrate (the current which flows between n-wells in a typical CMOS transistor).
    3. This substrate current ends up contributing to massive amounts of leakage current.

    I couldnt resist - the handy eq. from my VLSI Design for Deep submicron book says something along th
    • by jmv ( 93421 )

      1. Dropping Vdd to a CMOS transistors requires you to drop the threshold voltage to maintain performance.
      2. As the two voltages approach each other, theres an increase in the current in the substrate (the current which flows between n-wells in a typical CMOS transistor).
      3. This substrate current ends up contributing to massive amounts of leakage current.

      I suspect they work around that by using a High-k dielectric []. That means they can use a move a large number of charge carriers in/out of the channel without
  • And the ultimate in energy efficiency is ... the 0 Volt processor

    Yes, this marvel of technology will be completely silent, generate no heat whatsoever and emit no electromagnetic radiation at all. This bleeding edge device is so efficient that it requires no energy source.

    The only slight stumble block we are facing in the development of this wonderful device is the difficulty in determining which bits are set at 1 and which at 0 since the electrical level for both is the same. I'm sure further research wil

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