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Sun Microsystems Hardware

Sun Working to Eliminate Circuit Boards 349

lokedhs writes "Sun Microsystems is coming out with new chips without connectors. According to the article, this will have a lot of advantages: 'Performance, for instance, could greatly escalate because the speed of transferring data among chips and the number of channels for the transfers would increase. Energy consumption could also decline. Just as important, overall costs could fall, because defective chips could be removed like Scrabble tiles.' This technology will also lead to new CPU's without cache: 'The technique could also allow designers to remove the cache--the large pool of memory currently found on the processor--and put it on a separate chip. Caches were integrated onto processors to amplify bandwidth. Adding cache, however, bumps up manufacturing costs, as it greatly increases the number of transistors. With the bandwidth constraint gone, caches could once again be made independent without it having an impact on performance.'"
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Sun Working to Eliminate Circuit Boards

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  • Heat... (Score:4, Informative)

    by MojoRilla ( 591502 ) on Tuesday August 03, 2004 @10:35AM (#9868709)
    With so many chips so close together, they are certainly going to have heat problems.

    Interesting technology, thought.
    • Re:Heat... (Score:5, Insightful)

      by SatanicPuppy ( 611928 ) <Satanicpuppy.gmail@com> on Tuesday August 03, 2004 @10:43AM (#9868767) Journal
      Heat is solvable with next generation cooling (i.e peltier or cryo...or just a really big freaking fan) but the performance increase will have to validate the extra effort.

      The great thing about circuit boards is that they're cheap and easy to replace, so the maintenance gains they're talking about are not as great as they claim. It's also a VERY well understood tech; Sun takes a substantial risk by going in a totally different direction. It will be interesting to see how it plays out.
      • Re:Heat... (Score:5, Interesting)

        by johnhennessy ( 94737 ) on Tuesday August 03, 2004 @01:27PM (#9869875)
        Heat is really only a by-product of the problem. The main problem is power consumption. If you have a big enough fan you can cool anything (within reason) but who is going to buy a CPU that sucks 1KW (which is the way the power issues are leading).

        FYI: The power issue is only going to get worse at smaller geometries.

        Roughtly: Power = Switching Power + Leakage Power + Others.

        The two we are interested in here is the Switching Power and the Leakage power. Up until now Switching power has been the greedy party, but when geometries shrink down to 90nm and below, leakage power really kicks in.

        IBM and AMD have done some nifty stuff with strained silicon and silicon on insolutor to try and reduce the leakage power (and therefore the heat).

        So heat really will not be solved by just taking it away faster - because there's a whole lot more of it lurking around the corner, to fix the heat issue, you have to fix the cause not the symptom.

    • Re:Heat... (Score:3, Informative)

      by hcetSJ ( 672210 )
      They mention this (although they don't really address the issue):
      One of the chief difficulties in developing the technology comes from the environment where computer chips live. Heat and vibration in this environment can cause chips to get out of the precise alignment needed for proximity communication. Sun is currently tinkering with different techniques and different packages to prevent, or correct, these effects.
    • With so many chips so close together, they are certainly going to have heat problems.

      It's still a 2-D plane (I think), so it's nothing that a long heatsink and case fans can't handle.
  • Oversimplified (Score:2, Interesting)

    by Anonymous Coward
    This idea has merit, but the explanation is oversimplified. Moving the cache 2 centimeters from on top of the processor to a separate chip may be feasible, but it will increase latency (increasing the number of clockcycles a cache fetch takes and re-affirming a need for an on-chip cache to cache the "cache"). Other applications of this technology (like the fact that any part with issues can be easily replaced) seem more relevant.
    • Re:Oversimplified (Score:5, Interesting)

      by maraist ( 68387 ) * <michael.maraistN ... m ['AMg' in gap]> on Tuesday August 03, 2004 @11:14AM (#9868938) Homepage
      Shouldn't be a problem.. Have you seen the latency on modern Cache implementations? We're already at a BEST case of 2 clock delays with minimal concurrency. We're seeing 8 and even 16 clock cycle delays for L2 / L3 caches. Cache has always been hierarchical.. The lowest latency is always very small.. What this technology provides is effectively extraction of L2 cache with the complete transparenc y of adding L3 cache.. Think 128Meg L3 cache 8Meg L2 cache; something completely impractical for regular general CPU design.. Since you can "upgrade" your cache by replacing a peer-chip, now you can pay-as-you-go.. Spend a thousand dollars a year, upgrading one cache chip at a time.. And we've seen what's happened with the SDRAM market once commodetized. Pretty soon SDRAM may dissapear completely, being replaced by (albeit high power) gigabyte SRAM L4 modules.

      If cost effective, and if they can get past the alignment issues, this is spectacular.
  • by Anonymous Coward on Tuesday August 03, 2004 @10:38AM (#9868737)
    What they need, instead is VioletTooth (wireless chip-to-chip communcations). That way, they won't have to worry about alignment problems and such!
    • Im pretty sure thats nothing like what we need. We have protocols for short range RF communication that dont require careful alignment of the transmitter and receiver. Thats old hat. But to do what sun and other companies are proposing you would require a few dedicated chips for every few connections between individual components. The advantages of requiring alignment is allowing very low power since you dont need a strong signal and not requiring any sort of arbitration. Sort of like whispering a ques
    • It's an interesting thought - however if all these "pins" are transmitting in parallel, how do you tell one bit apart from the other?

      Imagine you have a 32bit data bus - in every single clock cycle, each of the 32 pins can change their state. If you receive a 0 from one pin, and a 1 from the other, how do you tell them apart?

      You can solve the problem by putting the data into a frame, building a checksum and discarding the frame - but that only helps if frame collisions are rare, if every single frame has

      • The solution to these problems are simple: you make the transmitters low enough power that they dont interfere with each other. From the Sun document I believe that the total power of each individual transmitter was on the order of 1-10 picojoules. That is precisely the reason alignment is such a prime concern - if the chips shift you have the wrong transmitters talking to the wrong receiver.
  • by Anonymous Coward on Tuesday August 03, 2004 @10:42AM (#9868761)
    Did you even read the article before posting it here. The article talked about eliminating the pin that is used to house the chip. Due to the size of the pins, it limits the number of I/O paths a chip can expose to the motherboard. Instead they can implement transmitter/receivers using capacitive inductence to increase the I/O paths a chip can expose. Thereby increasing the bandwith a chip can utilize.
    • by Anonymous Coward
      You mean this article?

      "There is a huge need for higher-bandwidth kind of chips," Robert Drost, a senior researcher at Sun Labs, said at an open house last week. "Rather than have the chips soldered onto a printed circuit board, the printed circuit board is taken out of the system."

    • by networkBoy ( 774728 ) on Tuesday August 03, 2004 @11:14AM (#9868940) Journal
      implement transmitter/receivers using capacitive inductence


      Ha! That's the funniest mis-use of electronics terms I've seen in quite a while.
      Yeah I know this is OT/FB but what the hell.
      -nB
  • by zaqattack911 ( 532040 ) on Tuesday August 03, 2004 @10:43AM (#9868764) Journal
    I figured Sun would have laid off their entire R&D department by now :)

    Love,
    Zaq
  • This wireless chips integrated for a purpose thing reminds me of Replicators [gateworld.net]

    Either way, I'm thrilled and spooked.
  • by xxxJonBoyxxx ( 565205 ) on Tuesday August 03, 2004 @10:45AM (#9868778)
    Um...who repairs motherboards anymore? At around $100 a pop, most people just get a new one.

    If there's a high-end application for this technology, great, but getting rid of high-end hardware is one of the biggest reasons people are also getting rid of Sun...
    • When things get old they become irreplaceable. I guarantee some mainframe in some bank or something out there somewhere has someone regularly soldering to it ;-) In many cases people repair the motherboards of their old rare computers like Atari's and Amigas. People repair motherboards, but people have a tough time repairing today's technology due to the size. It presents a challenge even to my $200 soldering iron. And I bet you a lot of manufacturers do bother to repair components that come back one w
  • Space (Score:4, Interesting)

    by SunCrushr ( 153472 ) on Tuesday August 03, 2004 @10:49AM (#9868788) Homepage
    One thing is for sure. If they can get this to work and if heat production can be cut down, this would make computing equipment and electronics much smaller. The printed circuit board is one of the big things holding us back from much better electronics miniaturization.
    • Re:Space (Score:3, Insightful)

      by doctormetal ( 62102 )
      One thing is for sure. If they can get this to work and if heat production can be cut down, this would make computing equipment and electronics much smaller.

      That is why this kind of technology [atmel.com] is used in embeded systems for years. Stack EEPROM and RAM on eachother in one housing to save space.
  • by !splut ( 512711 ) <sputNO@SPAMalum.rpi.edu> on Tuesday August 03, 2004 @10:49AM (#9868789) Journal
    Just as important, overall costs could fall, because defective chips could be removed like Scrabble tiles.

    With my luck I'll get a dead Pentium Z or Q that I just can't get rid of.
  • Prime Intellect? (Score:4, Interesting)

    by enyalios ( 686291 ) on Tuesday August 03, 2004 @10:49AM (#9868790) Homepage
    Wow, this announcement reminds me of an awesome book I just read: http://www.kuro5hin.org/prime-intellect/mopiidx.ht ml [kuro5hin.org]
  • Power (Score:4, Insightful)

    by pjrc ( 134994 ) <paul@pjrc.com> on Tuesday August 03, 2004 @10:54AM (#9868813) Homepage Journal
    Something that's probably been lost in the engineer -> marketing -> journalist translation is the need for power to be supplied to the chips.

    Most likely, the capacitive coupling of signals is only targeting chip to chip data signals, not the supply of power to the chips.

  • by Saeed al-Sahaf ( 665390 ) on Tuesday August 03, 2004 @10:54AM (#9868817) Homepage
    And in other news, scientists are developing a computer with no electronic parts at all [wikipedia.org]!
  • Eliminating connectors also removes a problem that pops up in microchips - without connecting wires, you don't have most of the parasitic capacitances that crop up on chips. A capacitor is anything with two metal contacts, so wires (especially parallel wires) cause very small capacitances, usually in the order of several picofarads. The problem is that on microchips, the capacitor values that are being used are generally in that range too, so parasitics can be very problematic.

    Heat transfer is also a pro
  • by Arethan ( 223197 ) on Tuesday August 03, 2004 @10:57AM (#9868837) Journal
    Dust & dirt. I would imagine that at such low voltage levels, induced current would require a damn near perfect level of alignment between the chip and the "socket". This is admitted in the article. What they don't admit is that it's going to be nearly impossible to get the damn thing in the socket without letting dust or dirt inbetween the chip and the socket.

    And a more interesting topic is their consistent mentioning of taking the cache of the chip. That's a nice dream and all, but where the hell are you going to put it then? Hardwired onto the motherboard? That's going to dramatically increase the cost of mobo's (so they are simply shifting who gets to eat the high sticker price on their products). And what if I buy a quad capable mobo, but only put 2 processors on it, I'm effectively wasting 2 sets of cache, rather than simply wasting 2 cpu sockets, and the sockets are a hell of a lot cheaper than the cache. I suppose you could fix this by going back to COAST (cache on a stick, yeah i know you remember that nasty stuff). But that brings in a whole new problem: These days, cache is only fast because it's so close to the cpu. If they move it off the die, it's just going to be put back on in 2 years because we can't access the cache fast enough ever since we moved it off the die.

    I'm no super computer engineer, but these guys better have an entire family of rabbits they plan on pulling out of their asses or this fucker's gonna flop.
    • by Anonymous Coward
      This is probably a fabrication tool - You buy a CPU that happens to be made from a handful of chips stacked and bonded together instead of the current monolithic silicon crystal you currently get. When you assemble it, you still have the contemporary packaging, its just that the manufacturer gets to do a bit more fine tuning with the manufacturing.

      For example, they might be able to tune a process to give higher yields on the cache and have a second process for the logic. Less broken chips, more stuff to se
    • The thing is cache latency is still for the most part pretty huge. With pipelines as deep as they are, the cache needs to be really huge to prevent stalls that will totally obliterate performance. Now, if you are able to separate the cache physically while not being restricted in the bandwidth between the external cache and processor by a lack of physical pins and the need for arbitration from other chips (the reason why external cache was so terribly slow) by using capacitive connections, well... the ga
    • by upsidedown_duck ( 788782 ) on Tuesday August 03, 2004 @12:02PM (#9869258)
      I would imagine that at such low voltage levels, induced current would require a damn near perfect level of alignment between the chip and the "socket".

      Well, if they invent a very good self-aligning mounting socket, dirt can be dealt with just by being very careful and using one of those air-in-a-can dusters. This technology would be very expensive, initially, so you could even get one of Sun's guys to come out and do it for you.

      That's a nice dream and all, but where the hell are you going to put it then?

      I'd bet they put it nowhere. L2 and L3 caches are a kludge, and, if they really achieve huge chip-to-chip bandwidth, they just might not need the cache hierarchy. This is reminiscent of old CPUs, where the system RAM ran at an acceptably large fraction of the speed of the CPU, so there was no L2 cache at all.
      • "I'd bet they put it nowhere. L2 and L3 caches are a kludge, and, if they really achieve huge chip-to-chip bandwidth, they just might not need the cache hierarchy. This is reminiscent of old CPUs, where the system RAM ran at an acceptably large fraction of the speed of the CPU, so there was no L2 cache at all."

        To me, it would seem like some sort of cache would still be needed. As I understand things, even if a slow bus was eliminated, it still takes the RAM much longer to look up data than the CPU is c
    • by Fished ( 574624 ) <amphigory@gma[ ]com ['il.' in gap]> on Tuesday August 03, 2004 @03:14PM (#9870839)

      Dust & dirt. I would imagine that at such low voltage levels, induced current would require a damn near perfect level of alignment between the chip and the "socket". This is admitted in the article. What they don't admit is that it's going to be nearly impossible to get the damn thing in the socket without letting dust or dirt inbetween the chip and the socket.

      It's called a clean room dude, and it's distinctly Old Tech. Granted, this will cut into the vision of pushing this out into the hands of field engineers, but I suspect that Sun is visualizing a "processor assembly" that will plug into an otherwise conventional motherboard. Perhaps in the distant future, that might change, but not now. What this ends up meaning is that they have two separate fabs making smaller chips rather than one fab making gigantic chips. It is much easier to make three or four small chips without errors than one huge chip, so they get higher yields for their processors. This means that they can produce a "processor assembly" with some ridiculous amount of cache and 8 cores for a much lower price than would be possible with conventional tech.


      And a more interesting topic is their consistent mentioning of taking the cache of the chip. That's a nice dream and all, but where the hell are you going to put it then? Hardwired onto the motherboard?

      The whole point of this tech is to directly connect the cache to the processor without putting it on chip. No, it won't be on the MoBo. Instead, it will be on the "processor" - but the "processor" will have multiple chips in it.


      I'm partially speculating here, but I bet that's what's on their mind.

  • Dupe (Score:5, Informative)

    by jdb2 ( 800046 ) on Tuesday August 03, 2004 @11:03AM (#9868851) Journal
    This was posted back in September of last year :

    http://slashdot.org/articles/03/09/22/1055244.shtm l?tid=102&tid=137&tid=187 [slashdot.org]

    jdb2
  • Same speed need? (Score:3, Interesting)

    by grunt107 ( 739510 ) on Tuesday August 03, 2004 @11:07AM (#9868881)
    With this connectivity, there would seem to be a need to standardize CPU chip speeds. Otherwise, a multi-CPU system w/disparate chip speeds would need a sophisticated register design to allow the faster chips to 'idle' while the slow one occupies a needed memory address.

    If designed, however, this could allow admins to assign quickie chips to the OLTP (or DSS batch loads @ night) systems, and the slower CPUs to the less intensive tasks (like sys admin).
  • Security (Score:3, Insightful)

    by nxcho ( 754392 ) on Tuesday August 03, 2004 @11:07AM (#9868883)
    Wow. It will be even easier to bug a computer, just drop a survailiance device in it, or near it (preferably with a small flashing led on it, to the Mission Impossible soundtrack).
    • > It will be even easier to bug a computer, just
      > drop a survailiance device in it, or near it

      And how are you going to interpret the signals? Humm?

      The idea is to replace the physical pins with capacitive coupling in order to _increase_ the desity. Ok, so we are already talking about several hundred pins on a modern CPU. If this technology works, that will jump up to a solid thousand. Then you start stacking them.

      So, even if your radio could detect a signal designed to be picked up by an adjacent

  • Seems like all that capacitive coupling would cause heat and e/m interference problems. Why couldn't you use LED lasers and sensors built onto the chips to optically couple adjacent chips through a simple optical connection? Each side of a square package could have a laser transmitter and a receiver so it could communicate with up to four adjacent chips. Dust in the sensors would be a problem. So would misaligned components. But, that would do the same thing, no?

    Just wondering 'cause, you know, I got no
    • Re:Lasers? (Score:2, Insightful)

      Well.... You can do that. And you can have a lot more than four interconnects per chips. However the "simple optical connections" are anything but simple. Look into (forgive the pun) photonic switching fabrics for more info. Cray Inc. is looking into optically coupled chips for their Cascade project (DARPA supercompute-off). Sun just thinks capacitive coupling is the way to go. As far as the heat goes... it doesn't generate as much heat as real connections, as little or no current is flowing.
  • by Anonymous Coward on Tuesday August 03, 2004 @11:10AM (#9868897)
    Well, this is offtopic, but there's no place to discuss the problems Slashdot has been experiencing, so why not here? If the admins won't provide an appropriate forum, we have no other choice.

    Does anyone have any idea what's going on here? I can't be the only one who wishes for a front-page story explaining why Slashdot is so amazingly unreliable and broken lately--especially for subscribers who are paying $ for this service.
  • by Anonymous Coward
    If you stack chips, then each chip can only communicate with chips right next to it (am I wrong?) So you'd be able to communicate directly with 2-6 chips, otherwise the chips would have to relay through each other, like a daisy chain. Hopefully none of them would break that communication, otherwise you could have a motherboard "chip" relay messages between them all.
  • by HotNeedleOfInquiry ( 598897 ) on Tuesday August 03, 2004 @11:11AM (#9868909)
    Let's see, in 2 weeks the've anounced that they were looking a buying Novell and getting rid of circuit boards. I guess a positronic brain will be next.
    • Let's see, in 2 weeks the've anounced that they were looking a buying Novell and getting rid of circuit boards. I guess a positronic brain will be next.

      They are getting out of hardware, buying a software house. What's next is getting rid of all the engineers (everything can be "outsourced"), and hiring a bunch of IP lawyers. We've seen this scenario, right?

    • I guess a positronic brain will be next.

      Yes, but it will be tied to their stock price, for very hard to explain technical reasons, so some days it will be called a negatronic brain. For the Trekkies out there, Data and Lore are really the same android, just in positronic and negatronic modes. Those scenes where they stand side-by-side...well, a wizard did it.
  • Important info (Score:5, Informative)

    by hcetSJ ( 672210 ) on Tuesday August 03, 2004 @11:12AM (#9868919)
    This makes the post make a little more sense, in my opinion (from the article):
    By contrast, proximity communication relies on capacitive coupling--the ability of two electrically charged devices close to each other to interact. Transmitters on one chip can send signals to another. These signals are then amplified. A much higher number of transmitter/receiver pairs than pins can be inserted in a specific area, which allows for more simultaneous connections.
    Can't get rid of the pins without replacing them with something else.
  • by El ( 94934 )
    Couldn't they solve the alignment problem with a tongue-and-groove type arrangement to keep chips from moving relative to each other? I knew all my experience playing with Legos would come in handy some day... now I can snap together my own computer!
    • Well assuming they put the chip's transmitters as close to each other as they used to with the pads for the pins - then the accuracy of the placement must be as high as the size of a pad + the distance between 2 pads. If that wasn't the case, the transmitter would align to another receiver.

      If you've ever seen a chip bonded to the carrier you'll know that the distance between pads is very very small - aligning these chips by hand would be impossible. (Also moving an actual chip die manually is difficult -

  • Some time back I posted this [halfbakery.com], of which the the present Slashdot Article reminded me. Some of it sound similar. And some is different, of course.
  • could this make the chips automagically scalable? could adding an extra 1GHz of processing power be like adding an extra stick of RAM?

    this kind of flexibility would be the only point going down this path imo.

    OT: why is slashdot's uptime now a matter of hours?
  • Looks like they could license this ARM style. There's a helluva lot of cross industry licensing, enforced by the ever popular Patent System.

    As an aside, I guess I'll have to stop Gaff Taping [webring.com] my CPU into the socket.

  • Maybe they could come up with a man who doesn't need a brain, and who lives without a pulse.

    Oh, wait, they did. Sorry, Darl.
  • Just like Legos (Score:3, Interesting)

    by Phat_Tony ( 661117 ) on Tuesday August 03, 2004 @11:25AM (#9869043)
    Maybe the next step is for all the components to come in lego bricks. The self-organizing bus won't care what order you put them together in, so whenever you add a component (50 GB flash drive, GPU, firewire ports, ect.) you just click it on somewhere, and it adds it into the system.
  • by TempusMagus ( 723668 ) * on Tuesday August 03, 2004 @11:25AM (#9869047) Homepage Journal
    Sun is the company I hate to hate. They have some of the brightest people in-house and create some amazing tech and ALWAYS seem to crap the bed on the business side. What good is a beautiful baby boy when it ends up being still-born? Man, I wish IBM just officially turn them into an R&D department.
  • by panurge ( 573432 ) on Tuesday August 03, 2004 @11:26AM (#9869052)
    Although they don't specify how this will work, it seems likely that the pins could be replaced with much larger conductors for power, ground and heat removal. With the existing multi-hundred-pin chips, many of those pins are for power and ground and have to connect to individual circuit board layers. Power devices, with few I/O connections, can devote an entire side of the package to ground or Vcc.

    As for the technique of capacitive coupling, that is how signals used to pass through low voltage amps virtually since the triode tube. The technique has been used for isolation amplifiers for many years. The signal on one side of the voltage barrier is digitised in some way (perhaps just PCM) and transmitted across a voltage barrier using very small capacitors, to where it is decoded. In some cases, power for the input side is also transmitted by capacitive coupling across the barrier.

    Because the transmitting and receiving side of the capacitors is so tiny and the electric field therefore so constrained, it is not going to be possible to read the signals with an external aerial.

    I believe Philips, among others, earlier suggested using LEDs and photodiodes along the edges of packages, but appart from requiring power they could only be unidirectional. Capacitive coupling itself absorbs begligible power and can be fully bidirectional.

  • early crays did this by layering chip on chip with metallic layer welding between the GaAs nuggets. that's why crays had to run in freon baths or liquid air. this can be expected to raise the price of sun servers built with that type of layering technology. substantially.

    isn't the market moving in the opposite direction, towards demanding cheap commodity solutions?

    just asking....
  • Isnt chips without connectors like write-only memory?
  • by Billy the Mountain ( 225541 ) on Tuesday August 03, 2004 @12:14PM (#9869372) Journal
    I wonder if this could lead to new treatments of spinal injuries? Say you could place a chip intervening between a severed spinal cord. Instead of having to physically attach all those millions of nerve endings, you could have the chip do it by proximity, and carry the signals on past the gap.

    BTM
    • Say you could place a chip intervening between a severed spinal cord. Instead of having to physically attach all those millions of nerve endings, you could have the chip do it by proximity, and carry the signals on past the gap.

      Nerve cells already work this way. There is no physical contact between the axons and dendrites. They come very, very close to each other. A potential wave (electric pulse) travels from the nerve soma down the axon, where it causes a huge number of neurotransmitter-filled vacuoles

  • by Animats ( 122034 ) on Tuesday August 03, 2004 @12:43PM (#9869555) Homepage
    The news article is useless. Read the technical paper [sun.com] and the patent [uspto.gov]

    Sun is not "coming out with new chips without connectors". Sun has demonstrated a new kind of interconnect in a lab. They might use it in a DoD funded supercomputer project. Maybe.

    You're not going to "stack chips like Scrabble tiles". The unpackaged chips have to be aligned within a few microns and held in position. That's going to be done in an IC packaging facility. The result will be a multi-chip module, a single package containing several chips.

    Multi-chip modules have been around for a long time. The Pentium Pro, for example, was a multi-chip module. There's a multi-chip module Linux computer in a single package [axis.com] from ETRAX. Multi-chip modules are expensive and hard to manufacture, and they're generally used only when you need to combine chips that couldn't be manufactured on the same substrate, like a fast CPU and flash memory. They usually cost more than the chips packaged individually. That's why this isn't a mainstream technology.

    This new approach might revive the multi-chip module market. Might. This has to become a cheap process before it will be used outside the supercomputer world. A whole generation of automated assembly machinery has to be developed to assemble and align chips in multi-chip modules before this is more than a demo technology. But this looks more promising than the way multi-chip modules are currently made. If it becomes cheaper to put two chips in one package than to put two chips in two packages, this is a significant development. Otherwise, not.

  • by PotatoHead ( 12771 ) * <doug.opengeek@org> on Tuesday August 03, 2004 @12:43PM (#9869558) Homepage Journal
    its negative effect on the market, read this one again and be happy.

    OSS is bringing down the overall value of computing, which is a good thing for all of us. The increased competition means the big players must begin to really innovate of die slow. The stuff we use everyday should be cheap. Intel did its job on the hardware side of things, OSS is working hard on the Software side.

    This is the Sun I am used to seeing. I have said before, their value is in their people --nice to see them putting it to use. :)

  • by CTho9305 ( 264265 ) on Tuesday August 03, 2004 @01:45PM (#9870011) Homepage
    There is a research paper here [sun.com] that gives a lot more information than the article linked (ironically enough, I happened to be reading it yesterday). They address many of the issues people have brought up (alignment, dust, etc.), and the paper really isn't a hard read.

    They actually have a bunch of interesting papers in the parent directory here [sun.com], mostly covering stuff about asynchronous/clockless computing.
  • Good for hobbyists (Score:3, Interesting)

    by heroine ( 1220 ) on Tuesday August 03, 2004 @02:28PM (#9870436) Homepage
    It would be good for hobbyists in that the shift to tighter pins and ball grid arrays is making it extremely expensive to fabricate single circuit boards. Imagine buying a bunch of ASICs from digikey, stacking them together with duct tape, and instantly having a custom circuit board. The sides of the chips would only need transmit, recieve, and clock plates.

    In manufacturing, the trend is still to integrate more and more on a single die. The cache will still be on the CPU but in addition, so will the system memory, graphics chip, and power supply. One day the 120V AC power cord will plug directly into the CPU.

  • by JonKatzIsAnIdiot ( 303978 ) <a4261_2000&yahoo,com> on Tuesday August 03, 2004 @03:04PM (#9870765)
    This technology pertains more to chip manufacture than motherboard manufacture. The alignment difficulties alone will prevent this from being seen in the field. According to the research paper [sun.com], the scientists first aligned the chips using a 10x stereo microscope, then used a Vernier measurement system to align them to within a few microns. There's no way that process will be seen outside of a lab or manufacturing plant.

    What this will let chip makers do is to manufacture the cpu and cache on separate silicon wafers, then stack them together and package them as a unit. The researchers claim a speed of 21.6 Gigabits/second using a 4x4 matrix of transmitters. Perhaps we'll see processors being sold with X Gig of memory on-board, with X being the amount of memory that can be manufactured in the same space as the CPU. Perhaps additional processors could be stacked together as well. Imagine putting 4 CPU's and 4 Gig of memory into a spot on a motherboard that takes 1 CPU today. You will still need a printed circuit board to connect to the circuitry that handles the external devices, ports, slots, etc.

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