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Hardware

Bright Peaks for Smaller Chips 42

Posted by michael from the tiny-bubbles dept.
Salden writes "University of Wisconsin scientists propose a way to create 20nm chip features. They were investigating the limits of X-ray lithography and discovered that they could control the phase of X-rays by adjusting the gap between a mask and wafer. Pretty cool."
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Bright Peaks for Smaller Chips More

Bright Peaks for Smaller Chips

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  • Ultrasmall chips (Score:5, Funny)

    by Sunnan ( 466558 ) <sunnan@handgranat.org> on Saturday January 18, 2003 @08:01AM (#5107235) Homepage Journal
    Just when you think they couldn't get any smaller than those annoying crumbs in the bottom of the bag. Why doesn't anyone make large chips? That would be easier to grab and eat.

  • Its not just the drawn length that matters (Score:5, Informative)

    by twfry ( 266215 ) on Saturday January 18, 2003 @08:08AM (#5107245)
    Already with 90nm processes, the height of the trans' gate is ~1.2nm. That's about 5-10 silicon atoms. The net result is you have to continuously lower the operating voltage to reduce current leakage. 90nm processes operate at ~1.0-1.5V.

    A drawn 20nm process will have an even shorter gate height. What would we be down to then? ~1-4 silicon atoms? This would force the operating voltatge to be lowered even more, possibly approaching Vt. (I forget exactly but around ~0.7V)

    I'm not saying that we'll never have a 20nm process, we will. But there is going to be quite a bit more involved than figuring out how to mask the waffer. i.e. double gates, etc.

    • Re:Its not just the drawn length that matters (Score:5, Interesting)

      by Anonymous Coward on Saturday January 18, 2003 @08:21AM (#5107263)
      you must be talking about high-Vt transistors. because operating speed is crucial, most state-of-the-art transistors have Vts around .3-.4 V.

      the smaller transistors will definitely lead to other problems for analog circuits. First of all, short-channel noise increases with maximum voltage decreasing, making it harder to achieve low noise figures.

    • Re:Its not just the drawn length that matters (Score:4, Informative)

      by Bender_ ( 179208 ) on Saturday January 18, 2003 @08:39AM (#5107285) Journal
      First of all, the parameter you are speaking of is not the "Gate height", but the gate oxide thickness. Dry oxidation allows very thin gate oxides, also below the current mark. Manufacturing these oxides is a comparably easy problem, however decreasing oxide thickness will increase the amount of current tunneling through the gate. This is going to be quite a problem in 65nm and below.

      To circumvent these problems there are a multitude of options under investigation, like high-k gate insulators, FinFets and more..

    • As the transistor gets smaller, more current will leak throught the thinner gate. One way to fix this is to use a high-k dielectric. This is not easy, the one single greatest thing about silicon that makes it so useful is its natural oxide, silicon dioxide. You basically put the wafer in an oven, and it grows its own dielectric on the surface. High-k dielectrics have to be applied in some way.
      -Brandon

  • Radiation Therapy? Or Spying!?!? (Score:5, Funny)

    by ackthpt ( 218170 ) on Saturday January 18, 2003 @08:31AM (#5107276) Homepage Journal
    They were investigating the limits of X-ray lithography and discovered that they could control the phase of X-rays by adjusting the gap between a mask and wafer.

    So when I had 6 weeks of radation therapy they could have been building a chip out of my own tissue to track me! That's all I needed to know. Packing bags for Idaho ASAP

  • What's next? (Score:2, Interesting)

    by Longjmp ( 632577 )
    What I'd be really interested in is what will be next in chip design. At one point traditionally designed chips will be at a single (or a few atoms per transistor) and shielding from natural radiation will be an issue, just as an example.

    Even if this wouldn't be an issue (I'm no expert,) there will be a physical limit.

    It seems that new designs are overdue. Quantum computers maybe?
    • It seems that new designs are overdue.

      That might come from Elbrus [elbrus.ru]

      Seems like an interesting article, especially the part about IA-64 and Transmeta.

    • Perhaps to overcome bit errors from radiation (natural or otherwise) we will end up with lots of error-correcting circuitry on chip. I believe that heavy-duty devices such as IBM's Power4 does.

      So we might end up with several ALUs on chip and a majority vote for the correct answer?

      Besides, the complexity of modern CPUs are already creating lots of problems which have to be solved today - eg: power and clock distribution. Both might be made easier with asynchronous logic but the only real investor/researcher in async is Sun Microsystems.

      Doubtless there is a huge amount of pressure for more CPU/RAM/etc... The majority will need it to run the latest MSFT Windows/Office combo at a fast enough speed to cope with someone typing at 25WPM or more... So one way or another, this technology will find its way into production, perhaps within the next 8 years.
    • At one point traditionally designed chips will be at a single (or a few atoms per transistor)

      I doubt that, it seems quite infeasible. IBM researchers are developing a technique to use individual atoms in a domino type setup to build gates, but it still requires more than a few atoms per gate (not really transistor based). Today's transistor's simply couldn't be built with a single atom. How do you have a gated channel with only one atom?

      As for quantum computing, researchers (also at UW) are currently developing a chip that would allow for a 1024x1024 array of quantum bits (I believe), which would be astronomically larger than any quantum chip ever built. The way it works is to isolate individual electrons by thick (atomicall speaking) barriers.

      I'm not sure quantum computing, however, will be able to replace current computing technologies as easily as a 'new design'. It is a fundamentally different thing, the majority of the algorithms we use today don't apply on quantum machines.

      A comment posted below this says something about multiple ALU's on chip voting to select the correct answer for error correction as if it's some sort of far of revelation. I can't say for certain, but I really wouldn't be surprised if this was already implemented. Consumer level chips have had multiple ALUs for different functionality for a long time, and the concept of two sets of the same logic computing a result and comparing them for error correction is a pretty fundamental error correction task.
  • Moore's law would appear to be alive and well.

    • Re:Moore's Law, anyone? (Score:1, Insightful)

      by Anonymous Coward
      Using phase of the radiation has been used for years with optics... if you look at the masks these days.. they only vaguely look like the actual layers... they take into account the edge diffraction and phase cancelation already... so really... nothing particularly new... just now they have shifted the frequency of the radiation..
    • And what happens when the smallest chip feature is a single silicon atom? What then? Huh? Huh?

  • Been done already (Score:5, Informative)

    by Snarfvs Maximvs ( 28022 ) on Saturday January 18, 2003 @11:43AM (#5107818)
    Numerical already developed phase-shift mask tech (http://www.siliconstrategies.com/story/OEG2001042 3S0029). Note that they could use 248nm tech to make 25nm features in 2001. Intel apparently licensed it 2 years ago!!!
    • Phase shift masking techniques have been in use for several years, and involve changing the transmissive properties of the reticle/mask material so as to shift the phase of light passing through select portions of the reticle relative to the clear areas. This process is done purely through mask design.

      The article involves a totally different concept, in which they are controlling the mask-to-wafer distance so as to control the phase of the light hitting the photoresist. Control of that mask to wafer distance in current technology is not rigidly controlled. It's considered fine to have the reticle in the same rough focal plane as the wafer, but not controlled tightly enough to keep phase polarity intact throughout the exposure field.

      It's an interesting technology demonstration, but I'm not convinced that it's adaptable to a manufacturing environment due to the amount of flatness variation on a local exposure field. Wafers may look flat, but on the transistor gate level, it's very lumpy. Sure, some areas of the field will be in phase, but other areas won't be in the correct phase spoiling the chances of getting a working circuit.

      It's easy to get a single transistor scaled to incredibly small sizes. It's another matter entirely to get an entire exposure field of consistently small devices, all of which work.

      Interesting article...

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