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Intel Hardware

Intel Cascade Lake-AP Xeon CPUs Embrace the Multi-Chip Module (techreport.com) 72

Ahead of the annual Supercomputing 2018 conference next week, Intel today announced part of its upcoming Cascade Lake strategy. From a report: The company teased plans for a new Xeon platform called Cascade Lake Advanced Performance, or Cascade Lake-AP, this morning ahead of the Supercomputing 2018 conference. This next-gen platform doubles the cores per socket from an Intel system by joining a number of Cascade Lake Xeon dies together on a single package with the blue team's Ultra Path Interconnect, or UPI. Intel will allow Cascade Lake-AP servers to employ up to two-socket (2S) topologies, for as many as 96 cores per server.

Intel chose to share two competitive performance numbers alongside the disclosure of Cascade Lake-AP. One of these is that a top-end Cascade Lake-AP system can put up 3.4x the Linpack throughput of a dual-socket AMD Epyc 7601 platform. This benchmark hits AMD where it hurts. The AVX-512 instruction set gives Intel CPUs a major leg up on the competition in high-performance computing applications where floating-point throughput is paramount. Intel used its own compilers to create binaries for this comparison, and that decision could create favorable Linpack performance results versus AMD CPUs, as well.

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Intel Cascade Lake-AP Xeon CPUs Embrace the Multi-Chip Module

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  • by Anonymous Coward

    Synthetic benchmark completely rigged to give Intel's kit an advantage does indeed give it an advantage, news at 11.

    • This. Also, "Intel forges ahead using their processor-specific compilers and instructions, ensuring their stranglehold over FPU instruction set adoption remains one generation ahead of the competition's ability to license access to said instructions."
    • Right, really just benchmarking AVX512 for a load that doesn't even make sense on the CPU, should be GPGPU. AMD will provide details on Rome (64 core Epyc) tomorrow, apparently. This is Zen 2 said to offer 13% IPC boost over Zen. When Rome comes out, Intel will most probably be a node behind for the first time ever.

    • by Agripa ( 139780 )

      Synthetic benchmark completely rigged to give Intel's kit an advantage does indeed give it an advantage, news at 11.

      Hey, if AMD wanted better results then they should have used their own compiler on Intel's benchmark. It is not Intel's fault that Intel's compiler selects what processor features to use based on CPUID rather than capability.

  • Times change (Score:5, Interesting)

    by Tsolias ( 2813011 ) on Monday November 05, 2018 @12:14PM (#57594326)

    A 1.5 years ago: Glued together CPUs BAD
    Now: Glued together CPUs GOOD

    • by Octorian ( 14086 )

      25 years ago... multi-chip module good.
      https://en.wikipedia.org/wiki/POWER2

      Seems like IBM had trouble actually fitting an entire POWER CPU on a single die back then. So they started with the CPU being a whole card of individually packaged chips, then later moved onto a multi-chip module. Makes me wonder if anyone else did the MCM thing, since I haven't seen non-IBM old computers taking that approach.

    • intel is losing big time to amd

  • Intel, circa 2017: "We cannot figure out how to successfully engineer 10nm wafers. Our tick-tock strategy is stalled, and we cannot design chips that are any faster. What should we do?"
    Intel Solution: "MORE CORES! [forbes.com]"

    Intel, circa 2018: "AMD just released Ryzen, and it's destroying us in benchmarks. Anyone figure out that 10nm thingie yet?"
    Intel Solution: "Nope. But we did add MORE CORES! [businesswire.com]"

    Now must be a great time to be an Intel engineer.

  • by sinij ( 911942 ) on Monday November 05, 2018 @12:32PM (#57594454)
    Intel says Intel CPUs are great. Yeah, what else are they going to say?

    It is all marketing hype until independent third-party bench-marking is done.
  • One of these is that a top-end Cascade Lake-AP system can put up 3.4x the Linpack throughput of a dual-socket AMD Epyc 7601 platform. This benchmark hits AMD where it hurts.

    Now let's see what it costs.

    • Let's see if they can actually make them. Intel's purported Threadripper answer i9-9900k is still out of stock. You can try a scalper for $1k. Then there are persistent tales of overheating, you can't cool it even with a normal water cooler.

  • by Joe_Dragon ( 2206452 ) on Monday November 05, 2018 @12:43PM (#57594548)

    how many pci-e lanes in 1 Socket and 2 socket?

    With AMD you have 128 with one or 2

    • by Agripa ( 139780 )

      how many pci-e lanes in 1 Socket and 2 socket?

      With AMD you have 128 with one or 2

      None, but they made it thinner, removed the analog headphone jack, and added a notch.

  • mac pro will have this late 2018 starting at 7-10K (dual cpu base with fully loaded ram channels and crap base video card)

  • by Luthair ( 847766 ) on Monday November 05, 2018 @01:01PM (#57594676)
    Specifically blocks non-Intel CPUs from getting an optimized code path, hardly shocking their CPU performs a lot better.
    • Actually, chooses a specially optimized path for GenuineIntel parts, and falls back to a standard path for non.
      Now I don't disagree with you that this sucks. However, I also think you're a disingenuous shit for wording it the way you did. Hurrah for the death of intellectual honesty.
      • by Agripa ( 139780 )

        Actually, chooses a specially optimized path for GenuineIntel parts, and falls back to a standard path for non.

        Now I don't disagree with you that this sucks. However, I also think you're a disingenuous shit for wording it the way you did. Hurrah for the death of intellectual honesty.

        Luthair was more accurate than you. Intel's compiler disables the use of features advertised by the processor in the feature flags like instruction set extensions if the CPUID is not GenuineIntel. The "standard path" is to ignore the processor features.

        After Intel lost the lawsuit over this, the court required them to advertise this fact which they did by posting a non-searchable graphics image with the text as a fuck you to the judge.

        • The "standard path" is to ignore the processor features.

          No, that is not how compilers work. Try again.

          • by Luthair ( 847766 )
            You need to do more reading friend. https://www.agner.org/optimize... [agner.org]
            • I'm very familiar with the lawsuit.
              The compiler works exactly as I said it did.
              The standard path excludes SSE support. If the runtime code detects a GenuineIntel part, it checks the CPUID flags to see if it has SSE support, and then utilizes the accelerated functions.
              As I said, you can argue all day whether that's crappy behavior (it's not like AMD chips don't have equivalent CPUID registers) but it is factually incorrect to say that they neuter code on AMD processors. They refuse to accelerate it on non
  • Does no one just ask - is this even a reasonable claim?

    Intel is going to be on an OLDER process node - their architecture is not running 340% faster than AMD.

    Intel is comparing their theoretical future chip with Epyc chips shipping now. https://www.newegg.com/Product... [newegg.com]

    Once these chips are available in quantity (they are not) drop them into some servers and start bench-marking them on performance per price /watt. And compare them to AMD chips coming out at that time.

    If this is the benchmark that is hitting

  • AMD schooled Intel.

Elliptic paraboloids for sale.

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