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Education Open Source Hardware Linux

Imagination To Release Open MIPS Design To Academia 63

Posted by samzenpus from the some-strings-attached dept.
DeviceGuru writes: Imagination Technologies has developed a Linux-ready academic version of its 32-bit MIPS architecture MicroAptiv processor design, and is giving it away free to universities for use in computer research and education. As the MIPSfpga name suggests, the production-quality RTL (register transfer level) design abstraction is intended to run on industry standard FPGAs. Although MIPSfpga is available as a fully visible RTL design, MIPSfpga is not fully open source, according to the announcement from Robert Owen, Manager of Imagination's University Programme. Academic users can use and modify MIPSfpga as they wish, but cannot build it into silicon. "If you modify it, you must talk to us first if you wish to patent the changes," writes Owen.
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Imagination To Release Open MIPS Design To Academia More

Imagination To Release Open MIPS Design To Academia

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  • It's very common these days for companies to allow universities to use their technology at the cost of tying the company into the university's patent revenue. And of course this is often publicly-funded research, so not only is the taxpayer paying for the development of patents used to sue that same taxpayer, the patents go directly to a company from academia.

    The net effect is to feed intellectual property centered companies at the expense of the technology sector in general and small technology companies

    • Re: (Score:2)

      by tlhIngan ( 30335 )

      It's very common these days for companies to allow universities to use their technology at the cost of tying the company into the university's patent revenue. And of course this is often publicly-funded research, so not only is the taxpayer paying for the development of patents used to sue that same taxpayer, the patents go directly to a company from academia.

      Well, it's "talk to us first" which probably means "if you want to patent this, you're going to have to license it to us" sort of deal.

      I mean, think a

      • The patent terms are whatever they want them to be. In general "reasonable" and "patent" don't happen together much. And "tiny", well I really doubt it.

        Having a company provide funds for a research grant and then reap the patent royalties isn't in general a good thing for society. The student researchers get paid like slave labor (if they get paid at all) and put what may be the best idea of their lives in some company's pockets.

        • I think you are painting an incomplete picture of what we have done here. Absolutely every university we've talked to has embraced this agreement with open arms. This package is mainly designed for students who are learning about computer architecture at the undergraduate/graduate level and who need lab support material for the course. Giving them access to the open RTL which they can study during their labs is in no way enslaving them to anything - they will be getting a chance to see how a CPU architectur

          • OK. Can we see your agreements, please? Because that did sound very much like trolling for additional intellectual property to add to your portfolio.

            People who read this article have pointed out three open CPU designs in addition to the one that I remembered.

            While your product might be "production ready", please keep in mind that open projects are very often written to a higher standard than commercial ones, and the researchers involved are no less professional than your own developers. And their projects c

            • Please understand that this is in no way trolling or any for of patent gathering/expansion. The reality behind this program was that teachers needed more resources for their coursework. We reached out to a few universities and everyone was very excited about using real RTL in their courses; for example, most computer architecture courses presenting RISC CPUs have a section on the load/store unit - once presenting the theory, being able to then point to the Verilog code and say "and here is how this is im

              • I found the commenter who posed this as a response to RISC-V interesting. The University of California at Berkeley has a completely public implementation, under the BSD license, without patents filed, which your effort appears to be positioned against.

                • There is a number of advantages of MIPSfpga over RISC-V including:

                  1. MIPS architecture is better supported by textbooks. It is used as the example of architecture _and_ an example of microarchitectural implementation in Patterson & Hennessy and in Harris & Harris

                  2. MIPSfpga shares Verilog source code with MIPS microAptiv UP - a commercial core that has many licensees including Microchip Technology. The university professors do have an interest to teach their students with an industrial core, not som

                  • I'm familiar with the Microchip implementation. This is a 300-MHz-class 32-bit processor. Not particularly modern and not really fertile ground for R&D.

                    We did have two or three suggestions from commenters of open MIPS processor implementations, some of which are more modern. One uses a proprietary high-level HDL, which I haven't investigated.

                    • Well, this core is useful for a number of student project. For example, the students can implement a multicore system on chip that consist of a lot of non-coherent cores for specialized computations. Or, for example, they can substitute L1 cache with their own cache that implements MESI protocol or some multicore coherency protocol they invent. Even for the basic course they can connect wires to the internal registers and observe basic pipeline execution.

                      Sure, you can do the same thing with educational subs

    • I don't think that your statement of a generality applies to the specific, Bruce. The modifier "if you want to patent the changes" must not be discounted. So if you write a research paper on how you can tweak their architecture to produce some feature, you can simply elect not to patent it. If somebody else tries to patent the same thing, even the company in question, your research is prior art that anybody can use to strike the patent down.

      As an academic who has done patentable research, I can tell y

      • You've made my point for me.

        And any informed patent holder knows that any violation must be prosecuted, or the validity of the patent evaporates.

        No, that's just the ignorance of the uninformed that "everybody knows", but it's wrong. You don't lose your patent from failing to enforce it. You might be confusing it with trademarks, which can go into the public domain if you allow them to become generic terms rather than specific brands. And you can sometimes lose the capability of being able to enforce again

        • You've made my point for me.

          And any informed patent holder knows that any violation must be prosecuted, or the validity of the patent evaporates.

          No, that's just the ignorance of the uninformed that "everybody knows", but it's wrong. You don't lose your patent from failing to enforce it. You might be confusing it with trademarks, which can go into the public domain if you allow them to become generic terms rather than specific brands. And you can sometimes lose the capability of being able to enforce against a specific infringer if you hold back until the market develops, that's the Doctrine of Laches. But you don't lose your patent. Nor would you lose your copyright due to failure to enforce.

          True you won't lose the patent, but there is a time limit on suing an infringer [cornell.edu], isn't there?

          Anyway, given that textbooks often discuss MIPS, good to see something being offered to Academia.

          • It is a time-limit on damages, which is not the same thing as a time limit on lawsuits. There is still the potential to restrain an infringer who started 6 or more years ago from further infringement through the courts - and totally kill their business - even though damages for the infringement can not be recovered. And you can sue any other infringer.

    • There is an alternative if one wants to avoid the strings Imagination has attached to the MIPS HDL sources. It's called OpenRISC, and it's from OpenCORES. It's based on the MIPS architecture, but has work-arounds around patented MIPS sections. Go w/ that if you want a fab to fab it out

      • It's not clear what version of the MIPS ISA they're implementing (the article I read just said MIPS32, which covers a whole range of things). It sounds like it's MIPS32r6, which is not backwards compatible with any previous MIPS version. The only value of MIPS over something like RISC V [riscv.org] (which is increasingly the standard ISA for computer architecture research) is that there's a large body of existing software for it, so you can do real evaluation.

        We've done a clean-room reimplementation of MIPS III (R4 [bericpu.org]

        • Does RISC-V follow the MIPS instruction set AT ALL? Or is it something invented from scratch? The site says variable 32/64/128 bit address space - does that mean the ALU and registers are statically or dynamically configurable to have variable lengths?

          • Does RISC-V follow the MIPS instruction set AT ALL?

            It's an entirely new ISA that is intended to be freely licensable.

            The site says variable 32/64/128 bit address space - does that mean the ALU and registers are statically or dynamically configurable to have variable lengths?

            There are 32-bit and 64-bit variants of the ISA (128-bit is coming). It also includes a variable-length instruction encoding (though currently all instructions are 32 bits) so that it's easy to extend (finding gaps in the MIPS opcode space can be challenging).

      • There is a number of advantages of MIPSfpga over RISC-V and OpenRISC including:

        1. MIPS architecture is better supported by textbooks. It is used as the example of architecture _and_ an example of microarchitectural implementation in Patterson & Hennessy and in Harris & Harris

        2. MIPSfpga shares Verilog source code with MIPS microAptiv UP - a commercial core that has many licensees including Microchip Technology. The university professors do have interest in teaching their students with an industrial

  • See OpenRISC [opencores.org], which IMO provides a better path for academia.

  • ...cannot build it into silicon.

    Isn't the whole point of an FPGA being able to "burn" a design into a chip rather than "building" it? Are they saying you can only run your modifications through a simulator instead of burning an FPGA to test it?

    If so, what's the point of the exercise? Wouldn't it make more sense to have students play with an open sourced or freeware design that they can actually implement and test?

    • FPGA is reconfigurable hardware.

      Verilog code in MIPSfpga is not FPGA-specific. It uses Xilinx and Altera macros for memory in caches, but with small modifications it can be used to make an ASIC.

      MIPSfpga has a clear path to commercialization. The main idea is: the students can play with the core, create multicore systems, modify caches, etc. If they invent something useful, they can attract venture investment, buy a commercial license for MIPS microAptiv UP and create their own ASIC design company.

  • I cannot see how you can be more dishonest, greedy and evil as a researcher. If anything in IP deserves to be called "stealing" then this is it.

  • This is a response to RISC-V (Score:1)

    by Anonymous Coward

    Berkeley University is pushing really hard to get universities to adopt RISC-V (an Open ISA and set of cores) as a basis for future processor and architecture research. The motivation behind RISC-V was to have a stable ISA that isn't patent encumbered, isn't owned by one company, and is easily extensible (OpenRISC didn't fit the bill here).

    I can see that ARM and MIPS would have a problem with this, especially as there is nothing particularly innovative or performance gaining about either ISA, and some recen

    • Repeating the AC because he's posted at karma 0. That's "University of California at Berkeley", AC, but the rest of this is spot on:

      Berkeley University is pushing really hard to get universities to adopt RISC-V (an Open ISA and set of cores) as a basis for future processor and architecture research. The motivation behind RISC-V was to have a stable ISA that isn't patent encumbered, isn't owned by one company, and is easily extensible (OpenRISC didn't fit the bill here).

      I can see that ARM and MIPS would hav

    • This is NOT a response to RISC-V; there are many good RISC architectures out there designed for academic purposes (and beyond) and RISC-V is definitely one of them. What this is: we wanted to give professors teaching the MIPS architecture access to real RTL.

  • This is great news. When I was in college the microprocessor design class used a variant of MIPS though this started the quarter after I took the class. In my class we had to wire-wrap a 16-bit MIPS-like CPU using discrete chips and a couple programmable ones. MIPS is relatively easy to implement for educational purposes due to the simple instruction encoding and clean architecture. MIPS, unlike some other processors like ARM, also allows you to add your own instructions using coprocessor 2 which can be a g

  • definition of 'open' (Score:3)

    by lkcl ( 517947 ) <lkcl@lkcl.net> on Tuesday April 28, 2015 @05:10AM (#49567339) Homepage

    Microsoft has an "Open License" which allows you to look at Windows NT source code. it's "open", yes? pay them $USD 1m per year, you get an "open" look at the source code of Windows NT. but if you ever dare to use it, talk about it, or do ANYTHING other than *read* it.... they will sue the fuck out of you.

    bottom line: can we PLEASE stop using the word "open" in context with these types of stupid, stupid proprietary arrangements? it really isn't helping.

    there are plenty of *LIBRE* licensed implementations of MIPS out there: many people have pointed that out (in comments i can see above this one), they're on http://opencores.org/ [opencores.org] - there are at least eight MIPS core implementations that i can see, there, possibly the best one (most complete) is this: http://opencores.org/project,m... [opencores.org] which has a 5-stage pipeline and a harvard architecture.

    so please, stop using the word "open" to refer to proprietary, restricted and patented material.

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