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Samsung Develops World's Fastest Embedded Memory With eMMC 5.0 Support 77

Posted by timothy
from the taste-just-like-the-others dept.
hypnosec writes "Samsung has announced the world's fastest NAND memory that supports the eMMC 5.0 standard. The new memory chips are based on 10nm class NAND flash technology and feature an interface speed of 400MB/s. Further, the 32GB and 64GB densities have a random read and write speed of 7,000 IOPS (inputs/outputs per second) while the sequential read and write speeds stand at 250MB/s and 90MB/s respectively. The chips will provide for better multitasking, HD video recording, gaming and browsing."
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Samsung Develops World's Fastest Embedded Memory With eMMC 5.0 Support

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  • by Anonymous Coward on Sunday July 28, 2013 @08:45PM (#44409153)

    And how many write cycles? HOW MANY CYCLES?

    • Re: (Score:2, Redundant)

      by Dunbal (464142) *
      At least 1?
      • At least 1?

        With new pre-loaded Premium Content from our Exclusive Content Partners, tedious "writing" is a thing of the past!

    • by arth1 (260657)

      Yes, that would be Useful Information.

      And also, what's the erase time?
      The main problem I have with modern NAND is the worst case latency, when a sector has to be erased - a 1 second hiccup isn't good, even if it only happens rarely.
      In short, I don't care about best times or average times, but want the worst time to go down, not up.

      • by unixisc (2429386)

        Erase times are always bad in flash - ranging in the order of seconds. Even in NOR flash it's bad. The only exceptions I've seen are Atmel's Di-NOR based flash - where they use 2 transistors per cell, which obviously reduces the capacity of the memory in the same lithography, and SST's SuperFlash, which is now a part of Microchip, and its original founders now running a company called Greenliant. But none of these products are NAND flash.

        The reason the worst times go up is die shrinks - in order to avo

    • by AmiMoJo (196126) *

      Knowing the number of re-write cycles alone isn't useful. You need to know how much spare capacity is available too, and if the controller does things like compression and caching.

    • by unixisc (2429386)
      Typically, any flash memory has 10k cycles per sector/block. Since you have a controller, it could do something like re-map writes to unused portions of the flash, so that sectors are uniformly written, as much as possible. So depending on how that works and how well they do it, one could multiply that with the number of blocks in the flash, and get an enhanced number for the total write cycles
  • hmm (Score:2, Redundant)

    by Trepidity (597)

    These numbers may not make sense to everyone and if we translate them to ‘English’, Samsung means that these chips will provide better multitasking, browsing, HD video recording, gaming, file transfers – all in all a performance boost as compared to today’s chips.

    A better translation could be to give me some information about what the current marketplace looks like. If it's the "fastest embedded memory", is that because it's 20% faster than the existing parts? 2% faster?

    • Re:hmm (Score:5, Funny)

      by Anonymous Coward on Sunday July 28, 2013 @09:26PM (#44409339)
      Well, let's say this Twinkie represents the normal number of I/O operations per second in the mobile arena. Based on this article's sample, it would be a Twinkie... thirty-five feet long, weighing approximately six hundred pounds.
  • Will they also provide a richer multimedia experience, more vibrant colors, and increased productivity? I hate these dumbed-down explanations of the benefits of some new computer technology.

  • by Anonymous Coward

    QUOTE "The chips will provide for better multitasking, HD video recording, gaming and browsing"
    Would anyone like to make an attempt to justify any of the above claims?

    -Multitasking? On a modern machine, this will be a RAM and CPU issue.

    -HD video recording? Yes, if you are Peter Jackson working on the next 'Hobbit' movie. For every ordinary users of HD video cameras, the camera pre-compresses the data stream to a level well below the memory bandwidth of existing high-end flash cards.

    -Gaming? SSD certainly do

    • I agree with your general sentiment, that the marketing puff piece is a marketing puff piece, and larded with nonsense; but it is worth noting that this is an eMMC part, not a chip destined to do the behind-the-scenes work in a SATA or PCIe SSD (though Samsung presumably has a design that exploits the same flash cells with a different interface either available or in the pipeline); which very strongly suggests that it's aimed at mobile devices.

      Compared to proper computers, even the latest mobiles tend to be

      • by Rockoon (1252108)
        SATA SSD's dont need faster flash at this time because the SATA consortium was too short sighted to see the need for a much fatter pipe, and because thats the bulk of the desktop SSD market, nobody is developing faster flash intended for desktop use. Mobil devices on the other hand...

        This will eventually bleed over into PCIe solutions, but its hard to imagine extensive assembly lines for the purpose.
        • This will eventually bleed over into PCIe solutions, but its hard to imagine extensive assembly lines for the purpose.

          Do we have server boards with flash slots alongside the RAM slots yet? That has to be coming - I keep hanging SSD's, which are mostly packaging, off of SATA cables for caching purposes and it seems silly.

          • I don't think that anybody has defined a special, application-specific, 'flash slot'; but pretty much all the non SATA/SAS drives (that you'd see in a server, things like this eMMC chip not so much) are just PCIe cards, and those are common enough, and often not otherwise occupied.

            It is true, though, that servers specifically built around the mechanical requirements of shoving a bunch of PCIe cards in are markedly less common than ones build around the mechanical requirements of shoving a bunch of HDDs in (

            • Honestly, why do we need a separate flash slot? It sounds like when Intel introduced the AGP slot, which is no longer there on motherboards today. The data transfer rates of PCIe is adequate for getting that data to the flash, which will in any case need some buffer chips in b/w, since there is no way NAND flash can such up data at PCIe rates. There have been, from what I understand, market research done into whether NOR flash should have a DDR like interface as DRAM does, but that's for applications lik

              • since there is no way NAND flash can such up data at PCIe rates

                That's the right metric - I was under the impression that some of the fancier NAND arrays (FusionIO and the like) were already limited by PCIe performance and could use faster access to the bridge for DMA purposes.

                It could be that I heard that story about PCIe2.0 though.

            • but pretty much all the non SATA/SAS drives (that you'd see in a server, things like this eMMC chip not so much) are just PCIe cards

              Right, and if you look at a 1U machine they have one or two of them on a riser card, if any. The same machine might have 8 2.5" bays in the front of it.

              the notion of using miniPCIe SSDs; that would be brutally expensive; but those things are only about the size of a DIMM, so even a 1U could accommodate pretty alarming capacity without using a proprietary form factor or socket

              • I imagine that the comparatively strict board size limit forces you to use the densest NAND packages to achieve reasonable capacities, and also limits the number of independent NAND chips you can have running in parallel behind your controller chip, so you may have to use faster NAND than some of the physically larger drives.

                Aside from that, and maybe a couple of extra PCB layers, I think that it's mostly a question of volume.

        • by AmiMoJo (196126) *

          To be fair SATA was developed at a time when faster speeds and smaller cables were required, but backwards compatibility and low cost were also primary considerations. PCI-e is a fundamentally different technology, designed mostly for throughput over short distances in an electrically controlled environment.

          In SATA's case simply increasing the bandwidth available is only half the problem. There is overhead and lots of signalling, with asynchronous operation of commands and the need for data integrity checks

          • by tlhIngan (30335)

            To be fair SATA was developed at a time when faster speeds and smaller cables were required, but backwards compatibility and low cost were also primary considerations. PCI-e is a fundamentally different technology, designed mostly for throughput over short distances in an electrically controlled environment.

            As was PCIe - it was designed in an environment where PCI was limiting - most PCI implementations were stuck with 32-bit 33MHz, despite enhancements to 100MHz (33/66/100), 64-bit, and other things. The p

        • by dfghjk (711126)

          The "SATA consortium" was far-sighted enough to know that pushing beyond SATA-3 speeds would simply be duplication of effort. The desktop market is not suffering from single pipes limited by 6Gb speeds and the eventual successor will be PCIe-based. The future of desktop storage is not obligated to be SATA and they know that. Apparently you don't.

          SAS is doing a 12Gb PHY, so if SATA turns out to want it, which they won't, it will be there to take. SATA3 will be fine for hard drives, SSD is better off on E

    • Multitasking: Swap. Notice that most applications on smartphones cease to execute when not actually on screen? The OS puts them onto flash to free up precious RAM. Not much RAM in a phone.

      HD Video recording: But now it doesn't need to compress it so much. Quality can improve.

      Gaming: Er, not so much. Faster level load times, but that's about it.

      Browsing: Now they are mostly making things up. I suppose it could speed up cache access, but that's hardly a bottleneck.

  • Such innovations are being made daily. It did not redefine computing nor is a leap signiifcant enough to close my other 12 tabs just to see this story :D I think I should stop giving Slashdot so much attention :P -- And I thought my jokes were bad!

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