Mass Production of 450mm Wafers Bumped Back Again: 2018 67
Taco Cowboy writes with news on the slipping schedules in the move toward both larger wafers and 3D integrated circuits in the semiconductor fab world. From the articles: "TSMC ... said it planned to start mass-producing next-generation 450mm wafers using advanced 10-nanometer technology in 2018. The advanced 10-nanometer chips could first be used in mobile devices and other consumer electronics, like game consoles, that demand high-performance and low power consumption. The plan was included in the latest technology roadmap unveiled by TSMC about one year after the chipmaker attributed its delay in making 450mm wafers, originally scheduled in 2015, to semiconductor equipment suppliers' postponement in developing advanced equipment for manufacturing amid the industrial slump. Chipmakers can get 2.5 times more chips from a 450mm wafer than from a 300mm wafer ... The industry's gradual migration toward 3D ICs with through-silicon vias (TSV) is unlikely to happen until 2015 or 2016, according to sources at semiconductor companies. Volume production of 3D ICs was previously estimated to take place in 2014. Leading foundries and backend assembly and test service companies have all devoted much of their R&D efforts to TSV development, and are making progress. The major players are believed to be capable of supporting 3D ICs by 2014, but the emerging technology going into commercial production may not take place until around the 2015-16 timeframe."
Probably one of the most interesting presentations at HOPE9, "Indistinguishable From Magic: Manufacturing Modern Computer Chips," covered modern semiconductor fabrication and why these things are cool. If you're interested in more background (what do all of those TLAs mean?), check out the slides / audio (or attached video of the presentation from YouTube).
It's all lies! (Score:3, Funny)
As we all know, however much They don't want us to, the pace of 'innovation' in semiconductor fabrication is based almost entirely on the reverse engineering of artefacts taken from crashed Grey spacecraft.
Unfortunately, a recent downturn in the tourism sector of Theta Epsilon Minus, caused by the booming popularity of direct neural hedonostimulator technology, has sharply reduced our supply of samples...
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It's pronounced: wauffer
Shameless Spam (Score:2, Funny)
Silicon Chips, Yum . . . (Score:1, Funny)
But
Prefer Nacho Cheese dip for my Silicon Chips
450mm (Score:1)
That's almost half a meter. That's gong to be one big CPU.
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the electricity resistance will be VERY LOW.
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the electricity resistance will be VERY LOW.
Resistance is futile. - The Borg
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Uh, it's wafer, not chip, size.
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And this, kids, is why it's important to get your units right. 1) It f*cks up your math, and 2) it opens you up to mockery.
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The units ARE right. The WAFERs will be 450mm. Today they are 300mm.
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The units ARE right. The WAFERs will be 450mm. Today they are 300mm.
Or 200mm, or 150mm... It really quite depends on the manufacturing equipment in the fab and the target market for the devices (not everything manufactured on a wafer is a "chip"). Rumors of 200mm's demise have been quite premature.
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Re:450mm (Score:4, Funny)
It's even more important when you attempt to mock people for wrong units when the units are actually correct.
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Intel's first 450mm wafer fab is set to open 2013 (Score:5, Interesting)
Called D1X (development, but also production like previous "X" fabs) in Oregon, with a second to follow. 450mm wafer production will likely hit volume levels by 2014, just not at the foundries listed in the story.
Price conscious, volume manufacturers like semi foundries would be more willing to push back adoption dates if the investment isn't likely to pay for itself. Most of their business is usually on n-1 or n-2 process nodes. This changeover just happens to be particularly expensive and may not yet make economic sense for another 2-3 years.
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Intel's R&D budget alone is around 70% of TSMC's total yearly revenue for example. Also, if you look up rankings of R&D spending by technology companies Intel's is basically the second highest just behind Microsoft.
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That's because Intel is years ahead of the other foundries and has been for some time. The spend countless billions a year on their fab processes.
Per Intel's January 2012 earnings report, their plan for this year is:
Capital spending: $12.5 billion, plus or minus $400 million
R&D spending: approximately $10.1 billion.
Which, compared to the size of my bank account, is "countless" :)
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you countless comment reminded me I guess
Re:Intel's first 450mm wafer fab is set to open 20 (Score:5, Interesting)
Now, there's been a big struggle between companies like Intel that wanted 450mm earlier, and the tool makers who sank a lot of money on the move to 300mm before and don't want to be burned again in the move to 450mm. The Intel announcement above was to put pressure on the tools providers. It didn't worked out in the end.
All this got sorted out between big boys recently, with Intel, TSMC and Samsung investing a lot of money in ASML to speed-up the availability of 450mm. But the accelerated roadmap has nothing to do with the announcement you quote, just look at it from ASML direct [asml.com] (slide 14). The 450mm process development tools are worked on starting mid-2015 and production equipment is available beginning of 2018. Exactly what is said in the TFA.
450mm is important as it is the only known step that will bring the cost of chips down. Other planned changes (finer processes, 3D chips...) increase performance but also cost. But 450mm requires huge upfront investments, so you need large volumes to recoup it and it will require a big upfront spending. Which is why a lot of people are pushing back. Intel has both high volumes, high margins and deep pockets so they're the most eager to get started. But as you can see, even with their backing it's not that simple and fast.
Re:Intel's first 450mm wafer fab is set to open 20 (Score:4, Insightful)
The lithography is one aspect but what about the deposition/etching equipment? It is spread across multiple vendors and getting them all to support 450mm is going to be one heck of a challenge when for the most part they have only just gotten 300mm production perfected. The chip manufacturers won't/can't settle for 450mm tools that don't hit or exceed the quality of work produced by current 300mm tools because the process nodes now depend on that quality to produce working chips. Maintaining anisotropic plasma etch selectivity or deposition thickness uniformity on over double the area without resorting to much slower processing is going to be a really tough target to hit.
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Exactly, once the wafer is chucked and aligned litho is really only concerned with little 40mm by 80mm blocks of the wafer and the rest is just step and repeat. Several years ago when I left the industry the 300mm litho tools were already fully capable of introducing exposure-by-exposure correction offsets, with different correction maps depending on what exposure system the wafer ran on for a previous exposure layer. However everything is always focused on the exposure side because they are the most expe
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No. D1X is just 450mm ready.
Similarly, I think the GlobalFoundries fab in Malta, NY is supposedly "450mm ready" or maybe the annex will be. But regardless, "450mm ready" doesn't mean all that much.
That would be interesting (Score:2)
It would be very interesting to have Intel running a 450mm wafer FAB when there is no one supplying the FAB machines !!
Of course 450mm is delayed (Score:1)
Re:Of course 450mm is delayed (Score:4, Informative)
Um, no. Larger wafers are a cost savings measure. 450mm means that you end up with fewer incomplete chips on the edges of your wafer, which in turn increases your yield. No one is stamping out a single CPU on a 450mm wafer.
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This is basically li
Re:Of course 450mm is delayed (Score:5, Insightful)
A standard die is 26x33 mm, which is much larger than the vast majority of the chips; most dies already contain multiple chips. Therefore, the edge loss is not as big a deal as you would think.
What is more of a cost saver is that most of the processing steps (applying photo resist, developing the resist, etching, ion implantation, annealing, and so on) are relatively easy to scale up to larger wafers, thereby reducing the process costs per unit of wafer area.
A big exception here is the lithography process, which gets significantly harder for bigger wafers, since it involves rapidly moving a wafer around with nanometer accuracy. A bigger wafer requires a bigger, stiffer, and therefore heavier wafer stage. ASML manufactures lithography tools that can do up to 175 wafers per hour [asml.com] (300 mm diameter) per hour, with an accuracy ("overlay") of 5.5 nm; that is about 3 dies per second. To give an idea of the scale: imagine that a vehicle is moving at 100 km/h, making multiple sharp turns per second, and tracks the ideal trajectory within 500 nm. And then the customer says: nice that you can do that with a sports car, but it's too small; can you build a heavy SUV that can do the same thing? (So there, a car analogy)
This is why Intel, TSMC, and Samsung have invested into ASML to speed up the development of 450 mm litho tools.
Disclosure: I work for ASML, but the above opinions are my own.
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No, three per second and that is a conservative estimate. 175 wafers per hour means 21 seconds per wafer and with 75 exposures on a wafer you are looking at around nearly four per second average, although some of those might be off the edge and not yield. The actual exposure speed is faster because there is some dead time when the wafer is not actively under the optics and exposing. Then remember that an exposure can have multiple chips in it (because no processor out there is 26mm by 33mm) and you will s
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The ability of the Twinscan to maintain the positional accuracy that it can at the speeds and accelerations involved is just jaw dropping. I'm sure they are telling you that you cannot do the logical thing to keep the forces manageable by dropping the scan speed much (if any) in the changeover from 300mm to 450mm because everyone would freak out as the whole point is to maximize exposures per second while minimizing wafer exchange time. I do think that other processes will also have some pretty awful tro
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Indeed; I guess we would feel sorry if the whole tool needs to be slowed down (reticle stage, source power, metrology) just because the wafer stage cannot keep up. The ambitions should be even higher: by the time that 450 mm tools go to the market, the overlay targets will likely
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450mm wafers don't mean 450mm products. It means you can fit 50% more chips onto a single wafer - you just upped your production rate by 50%. More than that, actually - because that's the diameter, not the area. The area just went up by 225%, assuming I did my math right.
A large chip right now is 150mm^2. So now instead of fitting 450 of them onto one wafer, you can fit 1000 of them. Bam. Productivity just doubled. Small CPUs are in the 70mm^2 range, and other chips are even smaller.
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It's 250% as the summary states. 50 x 50 is not 225.
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The diameter is increasing by 1.5 times (50% larger) the area is proportional to the radius squared so the increase is (1.5x1.5)= 2.25 times more area, 225% of the smaller size, or 125% more than the smaller size.
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Eventually this will be how Moore's law ends. (Score:2)
In a steaming pile of lies.
Eventually they will run into a technical problem that they can't solve. Marketers will continue to say 'it's all good, we're just pushing it back another year'.
I'm not saying this is the end. But it will eventually hit a wall.
Re:Eventually this will be how Moore's law ends. (Score:4, Funny)
Exactly! Why do some people even try and make things better? I mean, are they mental or something? We should gather up all these folks that won't give up and refuse to recognize the futility that is man and shoot them off on a rocket ship to another planet!
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Exactly! Periodic Table of Elements is complete! The party will be "soon". All forms of propulsion through the air has been figured out. DOD and DOE are cancelling all further ramjet experiments. All you science and engineering students in college? Shoulda' taken Post-Raphelite Literature, loosers!
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Everything has limits. When you approach the practical limits you don't already know the limit is there.
Everything is on time, until it is late.
Don't expect Intel to tell you 'we're hitting a technical wall' expect them to tell you 'it's going to take another year, but will be even better when we get there'. They have investors to manage.
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Just because da Vinci came up with the idea of the helicopter hundreds of years ago does not mean we shouldn't have worked atmaking it happen. Sure, some things are more difficult than others but that doesn't mean we should give up. Where would y'all like to live? A world where we only go after low hanging fruit or one where, despite many failures, we keep trying and improve on what we have done before?
Bottom line: On May 31, 2012, the International Union of Pure and Applied Chemistry (IUPAC) approved the a
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I do agree that there will come a point where no more shrinkage is possible - when we start getting into counting atoms, we're pretty much there. By then, hopefully, the market is also satisfie
Good; there's no need. (Score:3)
current wafers still yield large numbers of current-sized chips. and for the most part, chip architects are not primarily limited by available area: relentless process shrinks bring, if anything, more transistors than they know how to use. sure, you can always throw on more cache, especially L3. but the main issues today are power and IPC/TLP-type efficiency, not space. the K20 team at NVidia might disagree, but they _should_ be pushing the bounds, since their target is less cost-sensitive HPC, not commodity/gaming.
in short, the action is in litho, process, transistor topology, power and microarchitecture, not the number of chips spoiled by the edges.
Re:Good; there's no need. (Score:5, Informative)
That's correct for transistor-limited (aka pin-limited) chips, but not so for area-limited chips.
Yes, just like we have CPU-bound software and IO-bound software, we have area-limited and pin-limited chips. Pin-limited chips are where the I/O balls are keeping chips from becoming bigger - you see this as CPUs, SoCs, chipsets and other utility chips (many bus architectures are redesigned to be more conservative on their pin usage - why consume 64 pins when you can use 16).
Area limited chips are where the actual silicon area limits their usage - too big and flaws mean lower yields, too small and your devices may not meet requirements. These kind of devices are typically memory devices - the storage array is the largest consumer of area (the logic fits neatly around it) and the larger you can make the storage array, the bigger the memory.
Memory devices are also some of the most dense, transistor wise (a CPU has tons of "random logic" that means wiring is what keeps transistors spread apart, not transistor density). For a given process node, if you can double the area of the storage array, you double the storage.
And memory devices cover a wide gamut - from imaging devices (CCDs, CMOS), standard DRAMs and SRAMs, and EEPROM-style memory (including flash memory).
Basically the amount of storage you can stick is limited by area (double area, double storage, eseentially), but if you make the area too big, yields go down as the impact of an imperfection destorys the entire chip.
A larger wafer has more area available, and since wafer costs are mostly fixed (a single wafer costs anywhere from $1000-3000 or so), the number of good chips has to pay for it all. The more good chips (higher yield), the cheaper the cost.
A larger wafer means more chips can be made, so cheaper overall memory devices - which translate to cheaper SSDs, cheaper DRAMs, digital cameras with larger sensors, dSLRs with full-frame sensors at a budget price (this one especially - the sensor is the most expensive part because it's genuinely a HUGE piece of silicon and only a handful make it out of a wafer, even allowing for bad pixels).
For other chips, a larger area does allow for more wiring, which is what dominates chip design, not transistors. If you take something like an FPGA - the thing limiting it IS area - wiring area is extremely limited.
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Yes, just like we have CPU-bound software and IO-bound software, we have area-limited and pin-limited chips. Pin-limited chips are where the I/O balls are keeping chips from becoming bigger - you see this as CPUs, SoCs, chipsets and other utility chips (many bus architectures are redesigned to be more conservative on their pin usage - why consume 64 pins when you can use 16).
You sounds like a good advocate for TSVs. That said, defects in memory devices probably don't limit the maximum chip size all that much-- memory devices can contain lots of redundant elements to repair defects. Simple chips/wafer cost considerations--because no one wants to pay much for memory--probably has a lot more to do with it. It's just straight-up cost limiting area, not defect density. And when it comes to the push for 450mm, it's not necessarily higher yield that's expected, but lower cost per c
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The real advantage is that you produce more chips per wafer, and ideally, the per wafer processing time is unchanged, This has nothing to do with how good the chips are, or what they do. It is just to make more of them and make them cheaper.
I suppose if anyone really wanted to and could find the right equipment, they could m
No need. (Score:2)
If the move to bigger wafers is driven strictly by increased efficiency there's no incentive to rush to adopt it. It's no different than rushing out to buy a marginally more fuel efficient car. It's going to take years to make up the difference in savings, if that ever even happens.
The move to 450mm wafers is a massive investment. Twelve years ago I had the opportunity to visit a new 300mm foundry for TSMC's big Taiwanese competitor UMC. The entire line was built around that size; everything from the cases