MIT's Self-Assembling 3D Nanostructures — the Future of Computer Chips?

MrSeb writes "MIT has devised a way of creating complex, self-assembling 3D nanostructures of wires and junctions. While self-assembling structures have been made from polymers before, this is the first time that multi-layer, configurable layouts have been created, opening up the path to self-assembled computer chips. Basically, MIT uses diblock copolymers, which are large molecules formed from two distinct polymers (each with different chemical and physical properties). These copolymers naturally form long cylinders — wires. The key to MIT's discovery is that the scientists have worked out how to exactly control the arrangement of these block copolymers. By growing tiny, 10nm-wide silica 'posts' on a silicon substrate, the researchers can control the angles, bends, spacing, and junctions of the copolymer wires. Once the grid of posts has been built, the wafer is simply covered in the polymer material, and chip's wires and junctions self-assemble. The reason everyone is so excited, though, is that the silica posts can be built using equipment that is compatible with existing semiconductor fabs. Theoretically, chips built using this technique could have a much smaller feature size than the 28nm and 22nm chips produced by TSMC and Intel. According to Caroline Ross of MIT, it should be possible to build posts that are much smaller than 10nm."

One problem still unsolved

[girlintraining]

We can make it smaller, but we still can't alter the thermodynamics of the system: Specifically Black's Law -- the more current you pump into a given area, the more heat it's going to give off. Electromigration is a already a significant engineering barrier to further minaturization. Nanowires are going to break down even faster than existing circuit etchings.

I'm sure there's an EE reading this who can provide the grisly details of how circuit pathways would degrade, and the equations showing the reduced MTBF. But it's my lunch break right now, and I'm lazy. :)

let me understand it better...

[PaulBu]

... so, the claim is that one can build self-assembled circuitry, but you are still using 10nm "silica posts [...] built using equipment that is compatible with existing semiconductor fabs", i.e., you are still running your wafers through 10nm-capable semiconductor process for at least one step. If you have access to such a process, why not build wires using it as well, while we are at it?

Iast time I checked, metal ions in deposition chambers also "self-assemble" themselves into metal films, subsequently selectively etched and producing wiring on each and every chip currently made! ;-)

Paul B.