The Transistor Wars 120
An anonymous reader writes "This article has an interesting round-up of how chipmakers are handling the dwindling returns of pursuing Moore's Law. Intel's about four years ahead of the rest of the semiconductor industry with its new 3D transistors. But not everyone's convinced 3D is the answer. 'There's a simple reason everyone's contemplating a redesign: The smaller you make a CMOS transistor, the more current it leaks when it's switched off. This leakage arises from the device's geometry. A standard CMOS transistor has four parts: a source, a drain, a channel that connects the two, and a gate on top to control the channel. When the gate is turned on, it creates a conductive path that allows electrons or holes to move from the source to the drain. When the gate is switched off, this conductive path is supposed to disappear. But as engineers have shrunk the distance between the source and drain, the gate's control over the transistor channel has gotten weaker. Current sneaks through the part of the channel that's farthest from the gate and also through the underlying silicon substrate. The only way to cut down on leaks is to find a way to remove all that excess silicon.'"
Re:Leaking silicone... (Score:5, Informative)
That silent 'e' adds hydrogen and oxygen to silicon, leaving you with an insulator instead of a semiconductor.
Small 3D transistors (Score:5, Informative)
3D transistors aren't all that new; high power devices have been 3D for decades. Making 3D transistors this small is new. I wonder how long the lifetime is. The smaller the device gets, the worse the electromigration problem gets. The number of atoms per gate is getting rather small.
Note that this is different from making 3D chips. That's about making an entire IC, then laying down another substrate and making another IC on top of it. Or, in some cases, mechanically stacking the chips with vertical interconnects going through the substrate. The density improves, but the fab cost goes up, the yield goes down, and getting heat out becomes tougher. We'll see that for memory devices, but it may not be a win for CPUs.
Re:Small 3D transistors (Score:5, Informative)
3d integration should become practical when 3d cooling (channels? pipes? something else?) can also be easily integrated into the silicon. Once we can get the heat out, there's no particular reason that 3d can't *really* mean "3d integration", instead of "stack dies." I don't see any reason why this wouldn't come to pass. Even so, at the current geometries, we're approaching true high-performance systems on a chip.
Larger chips provide for more interconnects (more edge space) but at some point, that'll be overkill because the system will be all in there, and only I/O will need to be brought out. We're seeing it (in a kind of feeble way) with some of the microcontrollers, but I rather expect (ok, hope) that this will be how computers are supplied, or at least, one way they are supplied.
Re:Intel's 3g gate transistors stop all current (Score:4, Informative)
I think the point they're trying to make is that there's some sort of depletion going in the channel, which causes a very small, but not insignificant amount of current to flow from drain to source through the transition region in the substrate. From the standpoint that electrons are sitting on the upper part of the Si substrate underneath the channel, the summary makes sense. They want to remove the excess Si so that depletion mode current is more tightly controlled.
Re:Small 3D transistors (Score:4, Informative)
Larger chips provide for more interconnects (more edge space) but at some point, that'll be overkill because the system will be all in there, and only I/O will need to be brought out.
There's a little more to it than that. Larger chips draw a large amount of power (very suddenly) which means the number of pins used just for VDD + GND/VSS goes way up. That's especially true since more of the analog circuitry (notoriously sensitive to rail noise) would have to be integrated into the same chip within same process. That's just power, and depending on the application there's a lot more to consider for your pinout. You can really never have enough pins. That rule of thumb isn't going anywhere soon.
Re:Next up : Compiler wars! (Score:3, Informative)
The computer capable of that level of introspection and inference would snort at your silly fashion bias toward functional languages. The main calling card of functional languages is to offset weakness in human cognition. The human brain struggles to convert a functional specification into an optimal state machine without dropping a stitch. Kasparov and others complain about computer chess precisely because a well-tested adversary never drops a stitch, or so rarely that chess programmers have a dozens of other things to worry about first.
You do realize that the primary virtue of a functional language is purity in the specification domain and that it offers no fundamental advance in the execution domain?
There are two halves to the specification domain: algorithmic correctness, and shaping the performance/resource envelope. Prolog is a fairly reasonable specification language for algorithmic correctness, but almost completely useless at shaping the performance/resource envelope. Ever seen a smart phone OS programmed in Prolog?
There needs to be a word for this particular cognitive bias. This is the cognitive bias that if there's enough food on the planet, no one should starve, neglecting only the distribution challenge modulo politics, history, culture, and human nature.
In a world dominated by programming languages optimized for algorithmic correctness, all our problems will miraculously go away, because all those potent algorithms will sort out the performance/resource envelope without further input of blood, sweat, and tears. Nice vision.
That day will arrive when I specify the desired solution as a shortest path and the computer responds, "no can do, but would you settle for nearly as good almost all of the time under modest stochasticity assumptions in the underlying graph in near real-time to the largest feasible problem size as practically bounded by performance bounds elsewhere in the application feature set as they presently exist for the targeted user base?"
And I will go, could you break that down into smaller pieces? I'm out of practice thinking that hard.
On the transistor topic, it's kind of stupid to neglect the power distribution tree. Idle execution units don't leak if the master valve is slammed shut. In future we can have a much larger set of execution units optimized for different tasks, and only use the one that's needed for a heavy lifting loop.
You're already seeing the shift to dark silicon with the introduction of the ARM A5 as a companion dog to a bigger OOO furnace. One or the other CPU is shut off completely at any given time. Hard to leak power that never arrives.
Re:silicon-on-insulator (SOI) (Score:5, Informative)
You are not going to address Moore's Law with silicon -- the problem with silicon is that it has an effective 4 to 5 GHz barrier -- which is its dirty little secret that no one wants to talk about. The army had 100 GHz chips 20 years ago -- guess what, they weren't using silicon, but a germanium compound.
The only "real" solution is to start looking at other materials.
Re:New physical design. (Score:5, Informative)
Makes me wonder what one could do if you tossed traditional 2-D design (Most CPUs do have layers but very much 2D for all that) and went for a more 3D design like in the human brain. Create a miniaturized silicon 'matrix' of semi-conductor connections in a similar way to the human brain, for example.
The 2 main problems with 3d are currently fabrication density (defect issue,, stress, strain, etc) and how to get rid of all that heat. In your brain, that is solved by self-assembly, redundancy and low usage and a circulatory system. The current computing model of a usable CPU (runs an OS, does IEEE floating point arithmetic, does branching/looping) is probably too complex to solve this problem the same way in the forseable future. Of course if we change the definition of what a usuable CPU is, then perhaps this would be more feasable.
On the other hand there is some progress being made on bump stacked or through subtrate vias (TSV) assemblies (sometimes done for DRAM&Flash for cellphones) and even some limited 2-layered silicon devices (instead of the current one layer) of active devices per silicon die.
Stacked silicon die are promising, but there is currently a large overhead for mechanical connection between die so the density isn't very good. Also there's the problem of differing thermal expansion coefficients between the die that cause mechanical instabilities (which currently has to be solved by just putting in even more interconnect area overhead/margin).
The 2-layered devices are usually not done by stacking two active layers on the same wafer (because it's currently hard to grow a new thick uniform layer of silicon on top of existing circutry) , but they are made by patterning on one side, sticking a new clean wafer on top, flipping the stack over, shaving off the new top (used to be the bottom of the original patterned wafer), and then doing a new pattern on the newly shaven surface. As you might imagine, this isn't currently very scalable for more layers as defects will eventually dominate the system.
Neither technique is currently very good for getting the heat out.
People are working on this,and some limited stuff has made it's way out of the lab and into production but none of the 3d stuff is currently much better than just doing the standard planar chip for most typcial CPU projects right now. It's just a niche...
Re:silicon-on-insulator (SOI) (Score:3, Informative)
Germanium has been used in semiconductors longer than silicon, and it is widely used today. One of the emerging alternatives to silicon is a germanium-silicon alloy, that has been gaining traction from some years now, so this is nothing new.
Re:Intel's 3g gate transistors stop all current (Score:5, Informative)
SOI limits the depth of the conductive channel by placing a film on an insulator. If the insulator is low K Dielectric, the capacitance is reduced helping the speed. The 3D transistor on the other hand has a vertical fin of semiconductor created by etching away the surrounding material. This places the flat film of semiconductor on edge, then a wrap around gate applies the e-field on both sides and the top essentially surrounding the doped semiconductor path on 3 of 4 sides. This places all of the channel in close proximity to the gate voltage so a smaller voltage can pinch off the channel. SOI is still a gate on only one side (the top) of the semiconductor channel.
If you don't understand the tech, a photo is worth many words. A photo can be seen here.
http://www.pcmag.com/article2/0,2817,2384909,00.asp#fbid=2uqV-rrPnOE [pcmag.com]
Most people do not understand the photo. The center lattice structure contains 12 transistors. It has 6 parallel N channel devices in series with 6 parallel P channel devices. The semiconductor is the shorter fins under the higher fins. There are 6 of these fins with 2 transistors each configured in complimentary pairs as a basic inverter. The 5 bars on top are the Source on the ends and the Drain in the center and the two Gates in-between. The gate wraps the channel under it between the source and drain of each transistor. This is considerably different than SOI technology.
Xilinx are the leaders in transitor count at 6.8B (Score:5, Informative)
Virtex-7 2000T FPGA Device First to Use 2.5-D IC Stacked Silicon Interconnect Technology to Deliver More than Moore and 6.8 Billion Transistors, 2X the Size of Competing Devices SAN-JOSE, Calif., Oct. 25, 2011-- Xilinx, Inc. [design-reuse.com](Nasdaq: XLNX) today announced first shipments of its Virtex®-7 2000T Field Programmable Gate Array (FPGA), the world's highest-capacity programmable logic device built using 6.8 billion transistors, providing customers access to an unprecedented 2 million logic cells, equivalent to 20 million ASIC gates, for system integration, ASIC replacement, and ASIC prototyping and emulation. This capacity is made possible by Xilinx's Stacked Silicon Interconnect technology, the first application of 2.5-D IC stacking that gives customers twice the capacity of competing devices and leaping ahead of what Moore's Law could otherwise offer in a monolithic 28-nanometer (nm) FPGA.
Re:Small 3D transistors (Score:4, Informative)
Larger chips are also more expensive. A silicon wafer costs anywhere from $1000-3000 each. Each wafer has a fixed area, and the larger the chip, the less of them per wafer. Additionally, a larger chip means there's more of a chance of an imperfection in the wafer to destroy the entire chip, leading to lowered yields. Lowered yields meach the base price of each chip goes up as there are fewer chips to pay for the entire batch.
There are two kinds of chips - silicon-limited, and I/O limited. Memory devices (both volatile (DRAM) and non (Flash)) are silicon-limited - they are as big as economically possible (more area == more capacity after all) juggling yields and such to reach a usable price point.
CPUs are I/O limited - they are actually very small devices, the only thing keeping them back is the number of I/O pins. And it's not the actual silicon itself - it's the physical package that connects to the PCB. The most popular packages are BGA, but even those have specifications on ball size and ball spacing. Put the balls too close together and too small, and the cost of the base PCB holding the chip goes up significantly as the PCB has to be made to tighter tolerances.
Even so - we're talking about a thousand pins still in the latest high end Intel and AMD parts. This is doable as the PCB chip carrier can be made very specially (it only holds the chip, after all, and doesn't have to hold the rest of the circuits for the device) - basically it's a breakout board.
Comment removed (Score:5, Informative)