Multi-Core Voltage Regulators To Increase Processor Efficiency 64
cylonlover writes "For decades, chipmakers strove to develop the fastest and most powerful chips possible and damn the amount of electricity needed to power them, but these days raw grunt isn't the only consideration. As more and more devices go mobile and these devices become more and more powerful, chipmakers must also take the energy efficiency into account. Harvard graduate student Wonyoung Kim has developed and demonstrated an on-chip, multi-core voltage regulator (MCVR) that he says could allow the creation of 'smarter' smartphones, slimmer laptops and more energy efficient data centers by more closely matching the power supply to the demand of the chip."
Underwhelmed (Score:5, Informative)
I confess I am totally underwhelmed. Every chip I have designed since the 1990s (mostly wireless chips with embedded MCUs and DSPs, for portable applications) has had multiple voltage domains with multiple, independently controlled, on-board linear regulators -- sometimes as many as six or eight of them. Each MCU (and/or DSP) core always has its own regulator; it's the only way to meet the power budget of a mobile/portable product. Sometimes the voltage is dynamically controlled in response to processing requirements, and sometimes (if the processing requirements are relatively constant) the regulated voltage is designed to vary with temperature, so that at all times only the minimum voltage needed is supplied. (And yes, sometimes switching regulators are used, if the electrical noise can be tolerated in the application.)
ISSCC isn't known for accepting junk papers, so I'm hoping that what was actually presented (I didn't attend this year) was a novel on-chip voltage-regulation technique, and that the journalist has done a disservice to Kim by emphasizing the application, rather than the real novelty of his work.
The real problem with these designs is the interfaces between cores operating at different voltages. It's a PITA to do all the level-shifting to ensure that a core operating at 0.5 V can communicate with one operating at 1.2 V, ensure that one shut down doesn't affect one still operating, etc. There are lots of corner cases to consider (including transient effects while voltages and computing loads are dynamically changing), and a new technique to handle that reliably would be an advance in the art.