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Power Hardware

Multi-Core Voltage Regulators To Increase Processor Efficiency 64

Posted by Roblimo
from the now-we-need-multi-core-voltages-to-regulate dept.
cylonlover writes "For decades, chipmakers strove to develop the fastest and most powerful chips possible and damn the amount of electricity needed to power them, but these days raw grunt isn't the only consideration. As more and more devices go mobile and these devices become more and more powerful, chipmakers must also take the energy efficiency into account. Harvard graduate student Wonyoung Kim has developed and demonstrated an on-chip, multi-core voltage regulator (MCVR) that he says could allow the creation of 'smarter' smartphones, slimmer laptops and more energy efficient data centers by more closely matching the power supply to the demand of the chip."
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Multi-Core Voltage Regulators To Increase Processor Efficiency

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  • by arisvega (1414195) on Tuesday March 01, 2011 @04:24AM (#35345738)
    That's lame, even within their already lame marketing speech.
    • Re: (Score:1, Funny)

      by greatica (1586137)

      Don't you mean a "lamer" lame?

    • by gl4ss (559668)

      gizmag sucks, so does gizmodo and everything with giz.

      I fail to see the 'new' in this? were on-die dc-dc regulators impossible before? I find that hard to believe and per core sleeping etc too is such obvious things that I fail to see how thinking them up is revolutionary.

      • Yes, Gidget was always much hotter.
      • by skids (119237)

        I found the article interesting. Just because it's common sense doesn't mean it isn't worth doing a status report on the current state of progress in this area.

        True, some new non-SVR MEMs-ish converter would have been more exciting, but it's nice to know that there is still some efficiency/stability to glean from SVR technology.

      • by hitmark (640295)

        At least gizmag do not appear to have asshat writers that insert personal opinions into every story written.

      • by BillX (307153)

        True. On-die, per-core power management tightly integrated with what the CPU is actually doing is certainly a Good Thing (disclaimer: I design ultralow power / energy harvesting systems, so I'm biased ;-) , but you're right that here's really nothing 'new' here. Dynamic voltage scaling (many chips may safely derate voltage with lower operating frequency, and let the voltage sag much lower if they only need to retain memory contents) at the per-core or even on-chip-module level is already becoming a fad, and

    • by Gilmoure (18428)

      Would these be nerd smartphones?

  • Does anyone know of a good software solution until this kind of thing gets baked into the hardware?

    Right now I use RM Clock [rightmark.org]
    (which hasn't been updated since 2008)

    It drops voltages & multipliers lower than the standard intel/windows/BIOS options.

    • The process monitoring CPU usage could be swapped out while a process that requires high CPU usage and hence a higher voltage is swapped in. Of course it won't get the higher voltage until the monitoring process is swapped back and by then its too late. Catch 22.

      • It is possible to prevent specific parts of processes' memory from being swapped out.

        If it wasn't, the code that is responsible for bringing in pages from swap might end up swapped...

        • by Chris Burke (6130)

          They didn't mean "swapped" as in paged out to disk. They meant the OS scheduling other processes, "swapping" the context for that process in and swapping the context for the monitor out.

          To really take advantage of a regulator that can modify voltages in tens of nanoseconds, it's really going to take hardware monitors keeping track of activity on a very fine-grained level.

          Really I think that's fine. Software can handle the high-level power decisions based on what the chip is going to be doing over the next

    • by hairyfeet (841228)

      Uhhhh...why? Seriously both Intel and AMD have excellent power management and can drop the speed and thus voltage of cores not being used (I know AMD has had this since Phenom, I'm sure Intel has the same) and frankly if you really care about power usage not only do the default chips do a bang up job but both AMD and Intel offer ULV desktop and laptop chips that go even lower (AMD has the 610e which is a 45w max quad core, Intel I believe goes even lower) so honestly, what is the point?

      If they want to give

  • by YesIAmAScript (886271) on Tuesday March 01, 2011 @04:49AM (#35345818)

    Including the same charts and graphs.

    http://www.anandtech.com/show/1770 [anandtech.com]

    How this guy is going to get a patent on this stuff based upon his work in 2008 when Intel showed it onstage at IDF in 2005 is beyond me.

    • by tixxit (1107127)
      It varies the voltage to each core. If people can get new patents by adding "on the web" or "on a cellphone" to an existing technology, then I'd bet that this guy can get a patent by adding "for multiple cores".
    • by warrior (15708)
      Amd has been able to do this for quite a while as well. It was first featured in the Phenom quad core, which came out in 2007, so design work started much earlier.
    • by Lord_Byron (13168)

      Good point, the USPTO never flubs checking for prior art...

  • http://www.powervation.com/

    This company has a power control chip which has firmware which you can tailor to the hardware it is attached too. And its available to buy right now.

    • by Enigma23 (460910)

      http://www.powervation.com/

      This company has a power control chip which has firmware which you can tailor to the hardware it is attached too. And its available to buy right now.

      The reminds me of the Transmeta Crusoe [wikipedia.org] processor designs, which automatically shifted gears, moving the clock speeds up and down as more or less workload was put through the CPU.

  • Distribution (Score:4, Interesting)

    by MichaelSmith (789609) on Tuesday March 01, 2011 @05:29AM (#35345938) Homepage Journal

    So this is a way for an ALU (say) to send a message to to the MCVR saying "we need ten trillion electrons" when it is asked to a floating point multiplication, then the electrons get parcelled out and the ALU shuts down when the job is done. Sounds reasonable but there is still going to be a voltage regulator off the chip. This is more like an intelligent distribution system.

  • SmartReflex? (Score:4, Interesting)

    by queazocotal (915608) on Tuesday March 01, 2011 @05:48AM (#35345986)

    Sounds similar to SmartReflex (tm) which is shipping on millions of phones.
    http://focus.ti.com/general/docs/wtbu/wtbugencontent.tsp?templateId=6123&navigationId=12032&contentId=4609&DCMP=WTBU&HQS=ProductBulletin+PR+smartreflex [ti.com]

    Where it differs is that there is an on-chip regulator to do the dynamic scaling.
    The TI solution has a couple of regulators on-chip, with a couple of output voltages, as well as a more variable external solution.

    The above device has variable regulators on-chip. (for annoying technical reasons, these are linear regulators, not switching,
    so if they regulate to 50% output - half the (reduced amount of power needed) is wasted as heat.

    • for annoying technical reasons, these are linear regulators, not switching

      Because capacitors are bulky? I wonder if a regulator could be made to switch at a convenient frequency, perhaps by combining the power supply with the clock, if thats not too naive an idea about how these chips operate.

  • by serviscope_minor (664417) on Tuesday March 01, 2011 @06:03AM (#35346012) Journal

    CPU manufacturers have been caring about power efficiency for a vasy long time.

    In fact, the first version of the ARM processor (in the 80's) was designed around its power usage so that they could use a cheap plastic carrier, rather than a very expensive ceramic one like all the competeing chips.

    • At the data center end of the scale, the Power7 was only released in 2010, but the planning probably took a couple of years. It includes not only power control for each core, but the clever bit is the PowerProxy that helps pick a suitable level for each. There's a quick overview over at The Register [theregister.co.uk].

      Power6 (2007) had variable clock speed. Could you also adjust the voltage to each core? Is there a big advantage to reducing the clock speed if you don't also drop the voltage?

      • Giving an incredibly simplified equasion, power consumption is directly proportional to clock frequency, and proportional to the square of the voltage.
  • Underwhelmed (Score:5, Informative)

    by dtmos (447842) * on Tuesday March 01, 2011 @07:10AM (#35346222)

    I confess I am totally underwhelmed. Every chip I have designed since the 1990s (mostly wireless chips with embedded MCUs and DSPs, for portable applications) has had multiple voltage domains with multiple, independently controlled, on-board linear regulators -- sometimes as many as six or eight of them. Each MCU (and/or DSP) core always has its own regulator; it's the only way to meet the power budget of a mobile/portable product. Sometimes the voltage is dynamically controlled in response to processing requirements, and sometimes (if the processing requirements are relatively constant) the regulated voltage is designed to vary with temperature, so that at all times only the minimum voltage needed is supplied. (And yes, sometimes switching regulators are used, if the electrical noise can be tolerated in the application.)

    ISSCC isn't known for accepting junk papers, so I'm hoping that what was actually presented (I didn't attend this year) was a novel on-chip voltage-regulation technique, and that the journalist has done a disservice to Kim by emphasizing the application, rather than the real novelty of his work.

    The real problem with these designs is the interfaces between cores operating at different voltages. It's a PITA to do all the level-shifting to ensure that a core operating at 0.5 V can communicate with one operating at 1.2 V, ensure that one shut down doesn't affect one still operating, etc. There are lots of corner cases to consider (including transient effects while voltages and computing loads are dynamically changing), and a new technique to handle that reliably would be an advance in the art.

    • by Viol8 (599362)

      "It's a PITA to do all the level-shifting to ensure that a core operating at 0.5 V can communicate with one operating at 1.2 V,"

      Why should it matter? If the one operating at 0.5 gets 1.2 for a few microseconds what harm is done other than a bit more power used for that time? If the bit threshold is lower than 0.5 in both anyway then either voltage will register as the correct bit.

      • by dkf (304284)

        Why should it matter? If the one operating at 0.5 gets 1.2 for a few microseconds what harm is done other than a bit more power used for that time?

        IIRC, its going from the low-voltage to the high-voltage domain that's awkward; it's all too easy for the bits to not register properly. The other direction is no problem since you're going into a transistor immediately that is (of course) rated for the input.

  • by Anonymous Coward

    Lotsa fuzzyness in this blurb. Let's see if we can help clarify:

    (1) First, these are not "voltage regulators". in the usual sense of something that takes an unregulated voltage and provides a stable, regulated voltage. They're the opposite-- taking a relatively stable main battery bus and dropping it down to various lower and possibly varying voltages. The goal being to sacrifice some speed and noise margin in order to use less power.

    (2) Next: putting voltage droppers on-chip inevitably leads to mu

    • by arielCo (995647)

      (2) Next: putting voltage droppers on-chip inevitably leads to much lower efficiency-- the only way to efficiently drop voltage is to use a switching-mode regulator, which not only generates a lot of electrical noise, it requires a big hefty inductor and capacitor, neither of which can be made on-chip. This on-chip voltage-dropping scheme cannot be any more efficient that using a plain old resistor, where you end up wasting a lot of power to get to a lower voltage.

      You can have a big bunch of saved power regardless of the regulation scheme. It's all about the switching losses, v^2*c*f.

    • by skids (119237)

      it requires a big hefty inductor and capacitor, neither of which can be made on-chip

      According to the layout in TFA the caps are on-chip. Not all regulation schemes require an inductor -- depends on required parameters.

  • by jimmyswimmy (749153) on Tuesday March 01, 2011 @08:55AM (#35346566)

    Based on what gizmag presents I'm not terribly impressed. There are several reasons to put the VR offboard. First is space, second is heat. A VR consumes a lot of both (relative to a microprocessor). You can easily see >5" square of space and >10W of power dissipation next to the processor (and everyone cries about it because of its location).

    Since I don't see any resonant components included in the design it appears to me that this is a linear regulator, which will put out a lot of heat. In addition as it stands both Intel and AMD have the ability to dynamically scale the voltage they are being powered from. They can request a higher or lower voltage as well as (of course) draw more or less current, instantly, through their VID pins. So this sure doesn't sound like a great discovery, especially when you consider that the basic concept, as presented in the summary, is widely used and quite well known. But summaries by their definition don't tell the whole story, so perhaps there's more to it. I'll pull up the paper if it's available when I get to work.

    As chip-on-chip technology becomes more widespread I will be interested to see what happens. It seems like there may be a place for "on chip" (as far as the enduser is concerned) voltage regulation with some of these all-in-one converter MCMs.

    • The idea of using a linear regulator to save power is quite funny...

      Ok, it could lead to a linear reduction of power, since the processor will have quadratic savings, and the regulator linear increases. But it is still funny.

      • by Agripa (139780)

        The idea of using a linear regulator to save power is quite funny...

        At low enough input to output voltage differentials, linear regulators have higher efficiency than switching regulators.

    • by serbanp (139486)

      A VR consumes a lot of both (relative to a microprocessor). You can easily see >5" square of space and >10W of power dissipation next to the processor (and everyone cries about it because of its location)

      Totally wrong. You see, the VR's job is to transfer the power from a high(er)-voltage supply to whatever the CPU/GPU/blahblahblah needs. The switching VR's of today boast efficiencies in excess of 90%, while their load is a 0% efficient converter (everything the CPU eats gets transformed in heat). Which means that if the CPU dissipates 10W, the VR puts out no more than an additional 1.1W - peanuts. You have to design the cooler for the bigger pig, what the VR puts out is not significant.

      As for the FA, the g

  • Is this the classic head switch with feedback to adjust the output voltage? This kind of voltage regulator has been around for a long time, and is extremely common in embedded devices. You have the head switch there anyway for power collapse, just add some control to the gate voltage. Not terribly efficient, but you get increased R and so decreased V squared over R. Better than no regulation for small increase in area over what you had already (A big head switch).

    Perhaps it's yet another case of Acade

  • I am Wonyoung Kim, the PhD student who designed the chip mentioned in the article. I heard my work was mentioned in slashdot and wanted to clarify several points. - Per-core voltage control is not an old thing. Intel and AMD both do per-core frequency control, but not voltage control. Multiple cores share a single voltage in their processors. There is an opportunity for additional power savings if the voltage is controlled at a per-core basis to track per-core frequency changes. - My design is not a linear

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