Intel, Toshiba, Samsung To Form Chip Alliance 57
Lucas123 writes "According to a report from a Japanese news agency, semi-conductor leaders Intel, Samsung and Toshiba are forming a development alliance to halve the size of chip circuitry in order to create more dense NAND flash chips and more powerful processors. The vendors would not confirm the news report, but the Nikkei Daily said they hope to reduce lithography technology from the 20 nanometer size used today to something below 10nm. The news agency also said Japan's Ministry of Economy, Trade and Industry may fund up to half the project's cost, or roughly $61 million."
Halve the size of what? (Score:1)
Alliance? (Score:5, Insightful)
Or collusion?
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IBM+Toshiba+Sony = Cell (Score:2)
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Re:Alliance? (Score:4, Funny)
Then, what can we call the alliance between Samsung, Hitachi, Intel, and Toshiba? I'm sure someone out there can come up with a creative acronym.
I'll start. How about "THIS"?
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This shit hits this.
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Ah yes... I'm expecting Fujitsu, AMD, and NEC to form a rival alliance any day now.
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As long as it looks I'm paying the half without ever areeing to it, I'd say it is a swindle.
Oh yeah? (Score:2, Funny)
I'm forming an alliance with Pringles, Frito-Lays and Doritos!
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Those 3 have been conspiring in secret to fatten my ass for the last 15 years. Nothing new.
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Those 3 have been conspiring in secret to fatten my ass for the last 15 years.
Their considerable success in that project bodes well for this new effort.
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Those 3 have been conspiring in secret to thin my wallet for the last 15 years. Nothing new.
That's probably what you wanted to say . . .
And a side-deal? (Score:3, Interesting)
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An alliance of this sort most probably also means some price fixing deals already on the table. But if we get some decent capacity SSD's for reasonable price a bit sooner, for a few bucks more, I think its worth it.
Maybe. For <10nm MLC flash, I'd be impressed if the thing still has data on it by the end of the day...
doobietoker (Score:1)
embedded x86 (Score:1)
You want to embed x86?
For real?
Seriously?
You're not just joking?
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Halve, or quarter the size? (Score:5, Insightful)
Wouldn't this allow quartering the size, since you have this halving in both dimensions?
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I think personally the best idea is to use the highest dimension for the application. For example, when speaking of a 3D object, half the size would mean half the volume. Unfortunately, things like DPI don't work like that.
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Let's see... "Engineers are hard at work on new monitors with half the DPI of current monitors." Yeah, I see what you mean!
Let me see... "Indian Engineers are hard at work on new Chinese monitors with half the DPI of current Mexican monitors." Yeah, I see what you mean!
There, fixed that for ya!
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No matter what nationalities you use, it doesn't make sense to work on monitors with half the DPI of current monitors, does it?
Of course it does. $$$$$
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Half the DPI? You think someone wants 40 DPI monitors? Hey, the 80s called and they want their 40 DPI monitors back!
Of course it does, twice the monitors at twice the price. $$$$$ $$$$$
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Ha, screw that, we're halving our chips in the time dimension!
It's about time (Score:1)
Steve Jobs laughs derisively (Score:2)
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Intel at it again... (Score:5, Interesting)
Intel is starting to feel the heat from ARM. Sooner than later datacenters will be running on ARM processors, and doing the same work per time unit at a fraction of the power cost.
This is a new market that they wish to stomp on before it can get started.
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Bingo! Intel has nowhere to grow right except though embedded processors. And ARM stands in their way. ARM will be tough to beat, not only because of their low power designs, but the way their licensing works. You can turn your business over to Intel, or you can keep it inhouse via ARM.
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So now INTEL and the i86 are facing intrusion from the bottom, because the ARM cpu is a RISC design that provides better performance due to a more efficient architecture with fewer gates AT LOW POWER CONSUMPTION.
What are you talking about? ARM provides lower performance at lower power consumption.
I work on high performance clusters (usually SGE/ROCKS not Beowulf, sorry guys) dedicated to physical and biological simulations and there is just no chance the ARM is taking over. We are pushing the bounds of our chips (all Nehalem-based Xeons) already, going to back to PIII-era performance would be a huge setback. There's just not a lot of competition with superscalar out-of-order x86-64, although specialized machines a
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The key word here is efficient. Specifically I am talking about operations per watt. If some combination of heat dissipation and cost to run the system are limiting factors, then this kind of efficiency is important.
I am not the only one who thinks this way. IBM has also made a system that chose lower power CP
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I love my Nexus One too, but there are limits.
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The key word here is efficient. Specifically I am talking about operations per watt. If some combination of heat dissipation and cost to run the system are limiting factors, then this kind of efficiency is important.
But in the HPC world, the real limiting factor is the interconnect and the software interface. The interconnect latency determines how large of a job can finish in reasonable time, and is a fixed (high) cost per CPU. Meanwhile the software interface determines what off-the-shelf software will work with minimal investment. It's not worth spending programmer ($100k/year) or even graduate student ($40k/yr) time chasing a few watts when you have funding agencies expecting actual scientific results in the next q
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In parallel applications the total performance per watt, among all ores, is what counts. Today, you can take a number of ARMs and equal the performance of the intel solution at a lower total wattage.
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INTEL, AMD and other i86 vendors were able to fight back by using RISC internally in their micro-architectures
This is a massive oversimplification. RISC and CISC chips used similar execution units, but RISC had simpler instruction decoders. With early RISC chips, this was a significant advantage because the instruction decoder took up an appreciable fraction of the die area and it meant that, with the same transistor budget, RISC chips could have a lot more execution units.
This advantage became less pronounced over time, because the space needed for the instruction decoder was fairly constant, while the total t
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Intel is starting to feel the heat from ARM.
Wait, I thought heat comes from Intel, not from ARM.
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Oh no (Score:1)
Do you want to form an alliance with me? (Score:1)
Samsung is also a member of the ... (Score:1)
Common Platform Alliance - IBM, Global Foundries (you know, the former fabs of AMD), Samsung. Chartered, now part of Global Foundries, was a member too.
So, Samsung must be giving some kind of assurances to Intel they're not going to let ideas and techniques spill over into the Common Platform Alliance...