Intel Shows 48-Core x86 Processor 366
Vigile writes "Intel unveiled a completely new processor design today the company is dubbing the 'Single-chip Cloud Computer' (but was previously codenamed Bangalore). Justin Rattner, the company's CTO, discussed the new product at a press event in Santa Clara and revealed some interesting information about the goals and design of the new CPU. While terascale processing has been discussed for some time, this new CPU is the first to integrate full IA x86 cores rather than simple floating point units. The 48 cores are set 2 to a 'tile' and each tile communicates with others via a 2D mesh network capable of 256 GB/s rather than a large cache structure. "
Meh. I'm holding out for a kilocore. (Score:2)
...or perhaps a megacore?
48 is sufficient for most Ph.D. dissertations. (Score:5, Interesting)
Unlike Stanford University, UCSB lacks the money to build a full-blown multiprocessor system. If UCSB had such a system back in the 1990s, then UCSB would likely have produced as much multiprocessor research as Stanford University.
This 48-core processor chip, due to the fact that it will eventually be a commercial product mass-produced by the millions of units, will be economically cheap. This chip will enable UCSB to build or buy a cheap multiprocessor system.
A bunch of graduate students is already salivating at the prospect. They are drooling.
Rather than Larrabee, Intel should've focus on CPU (Score:2)
Intel ought to focus. They need to focus more on CPU rather than Larrabee, which is an obvious mistake.
Re:48 is sufficient for most Ph.D. dissertations. (Score:4, Informative)
Actually, UCSB had exactly such a system in the 90's, called Meiko: "The Department of Computer Science at UCSB purchased a 64-processor CS-2 in June 1994." [ucsb.edu]
Re:48 is sufficient for most Ph.D. dissertations. (Score:5, Funny)
Word gets pretty slow when you hit a hundred pages with figures on a Core Duo, but you could always just use LaTeX or a file per chapter. I managed to get my dissertation done with just two cores and my parents managed with a typewriter (although those were masters, not PhDs).
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That's pretty funny.
Made me think about how I created beautiful reports, using LaTeX, on a simple 100 MHz Pentium machine running Slackware Linux. Now there's Office 2010 coming up, and I'm not sure what the system requirements are, but I'm pretty sure it doesn't do ligatures [wikipedia.org].
(Ligatures: when you write "finally", the dot on the i looks funny next to the top of the f, thus LaTeX creates one specially designed character, a ligature, just to make it look good.)
Re:Meh. I'm holding out for a kilocore. (Score:5, Funny)
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Advantages over just adding more FPUs? (Score:2)
Can someone elaborate on why you'd want 48 full processors, rather than a processor with two (dual) or four (quad) "cores" (I'm presuming core in this case == FPU in the article). Supposedly Win7's SMP support becomes much more effective at the 12-16 core thresehold.
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For a server.
Probably not running windows, as linux and other *n.x type OSes support monstrous amounts of CPUs already.
Idle benchmarks (Score:5, Insightful)
With 48 processors you can have your system 98% idle running your typical application at full speed rather than just 50% or 75% idle as is the norm now.
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Please tell me where I can find boxes that would run 50% idle for my use. My company would pay handsomely for such CPUs. Current Quad Xeons fail to do this.
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Yes. Serial RAM acces. Damn. When are people going to realise that RAM, which has a lot of, what are they called, banks?, hysically seperated from each other, could be made paralell?
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So why not multiple busses to the CPU?
Re:Advantages over just adding more FPUs? (Score:4, Informative)
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Multiple channels and overlapped memory access? The hardware does it automatically. No need to program anything different (well, I guess there is BIOS code somewhere that configures all the channels and bank information - but most people shouldn't see that).
Now, programming a 48 core FPU monster? That is a much harder problem!
Re:Advantages over just adding more FPUs? (Score:4, Interesting)
GPUs are using 256 bit wide data paths now to improve data throughput; I think it is only a matter of time until the memory bus is a whole cache line (256 bits?) in width, enabling read/writing of entire cache lines in a single operation. Seems simple to me, but your pin count and power usage go up, as well as the number of separate DRAM chips you need for a wider memory bus.
Re:Advantages over just adding more FPUs? (Score:4, Interesting)
A cache line on a modern Intel/AMD processor is actually 512 bits, or 64 bytes.
A memory bus 512 bits wide wouldn't really help much, though -- right now when dealing with memory, most of the time is spent in the various latencies. When you are fetching a lot of memory sequentially, you can get insane speeds even today. But that's not how you usually read memory -- instead, you read a few words from different locations, and the memory controller needs to activate the correct bank, row and column before you get what you need. On typical PC-10600 DDR3, that means at least 15 bus cycles just waiting around for the memory to adjust. Making the bus 512 bits wide would speed up the actual transfer to one bus cycle from the 4 what it takes currently, but that would only mean an improvement of about 15% -- at a huge cost for having to accommodate those 384 extra data lines on the chip, socket, motherboard and ram. It's better just to try to speed up the memory so burst transfers happen "fast enough".
I don't know about nvidia cards, but at least for ati the card doesn't actually have a 256 bit memory interface -- instead, it has 4 completely separate 64-bit memory channels connected to a fast ring bus. The interleaving of data on those separate memory channels is done very coarsely -- basically, entire textures and such are allocated on a single channel. This means that when that texture is being fetched, the 3 other channels can serve other requests.
This is the way I see cpu's evolve too -- even on current hardware, namely phenom 2, you get better performance when you ungang the memory channels, and wait 8 cycles for a single memory transfer instead of 4, because that way you get to wait on separate latencies on the separate channels at the same time. Of course, in the perverse case all the data you want to access resides on one of the channels, but the chance of that happening by accident is pretty much nil.
Re:Advantages over just adding more FPUs? (Score:4, Informative)
On any vaguely recent non-Intel chip (including workstation and server chips for most architectures), you have a memory controller on die for each chip (sometimes for each core). Each chip is connected to a separate set of memory. A simple example of this is a two-way Opteron. Each will have its own, private, memory. If you need to access memory attached to the other processor then it has to be forwarded over the HyperTransport link (a point-to-point message passing channel that AMD uses to run a cache coherency protocol). If your OS did a good job of scheduling, then all of the RAM allocated to a process will be on the RAM chips close to where the process is running.
The reason Intel and Sun are pushing fully buffered DIMMs for their new chips is that FBDIMMs use a serial channel, rather than a parallel one, for connecting the memory to the memory controller. This means that you need fewer pins on the memory controller for connecting up a DIMM and so you can have several memory controllers on a single die without your chip turning into a porcupine. You probably wouldn't have 48 memory controllers on a 48-core chip, but you might have six, with every 8 cores sharing a level-3 cache and a memory controller.
Re:Advantages over just adding more FPUs? (Score:5, Informative)
Re:Advantages over just adding more FPUs? (Score:5, Informative)
Re:Advantages over just adding more FPUs? (Score:4, Informative)
Cache coherency should be handled by the programmer, not by the hardware. Cache coherency protocols consume more bandwidth the more cores you get. The more cores you get, the more important that bandwidth becomes. At some point Cache coherency will become a bottleneck. We've been holding quite well to doubling transistor count every 18 months. If we suddenly go from strong single cores to somewhat weaker multi cores, not only will they pack more cores in for the same transistor count, but more transistors.
Imagine, our 4 core cpus will be 8 core in ~18months, then 16 ~18 more month. Intel has hyper-threading and AMD has a similar thing, so now it's like 32 cores. So, in ~ 3 years, at our current rate, we could have 32 logical CPUs reporting for low-mid sub $1.5k computers
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Yes. YES! Raytracing! And emulating a D3Dn card in software (Google: pixomatic) and run the latest game with acceptable framerates.
Re:Advantages over just adding more FPUs? (Score:5, Insightful)
Can someone elaborate on why you'd want 48 full processors, rather than a processor with two (dual) or four (quad) "cores" (I'm presuming core in this case == FPU in the article).
Bad assumption. In this case, we're talking about (what you would consider) a 48 core CPU. Previous designs would have apparently contained only a small number of full processing cores, and a large number of parallel units suitable only for floating point calculations (which can be great for various types of scientific calculations and simulations). This new design contains 48 discrete IA x86 cores.
Seems like the type of processor Grand Central Dispatch [wikipedia.org] was designed for.
Yaz.
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The worst thing about his assumption is that it is wrong. But that is sufficient to make it bad.
This is simplistic and wrong. It is true that fewer cores implies less inter-core communication, but this is not a design criteria for putting fewer cores in a system. While it is true that having
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webserver on a high traffic site. Either serving up lots of db connections or a lot of http connections, either way, I can imagine this having specific uses.
Re:Advantages over just adding more FPUs? (Score:5, Interesting)
Can someone elaborate on why you'd want 48 full processors, rather than a processor with two (dual) or four (quad) "cores" (I'm presuming core in this case == FPU in the article). Supposedly Win7's SMP support becomes much more effective at the 12-16 core thresehold.
The first thought comes to mind if video processing and CGI animations because those applications are embarrassingly parallel [wikipedia.org].
And those companies usually have the money to spend on top of the line hardware.
Eventually this will trickle down to consumer level as always and people at home can now do real time movie quality CGI on their home computers in 10 years.
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Embarrassingly parallel is right. Cache coherency was sacrificed in order to up the number of cores, though I suppose a Beowulf on a chip is still useful for some things.
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I was recently reading an article about multi core designs and they said they'll have to drop cache coherency at some point soon and redesign locking a bit. Some other architectures don't use cache coherency to help with scaling, but that's not x86.
NUMA vs SMP (Score:3, Interesting)
In my experience Windows 7 64 bit is noticeably faster with NUMA configuration (Windows experience index is significantly higher because of improved memory throughput) and majority of application also run up to 10 % faster.
I don't know if this is because of Nehalem Xeon CPUs having faster access to CPU local memory in NUMA configuration or if windows is also optimized for this?
Yet another cloud? (Score:5, Insightful)
Why is everything called cloud these days? Yet another du jour buzzword. Is this really justified here?
Re:Yet another cloud? (Score:5, Insightful)
When it comes to marketing cliches, when it rains, it pours.
Re:Yet another cloud? (Score:5, Funny)
Why can't it just be cloudy?
sorry.
Re:Yet another cloud? (Score:5, Funny)
I don't have the foggiest idea.
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The term "cloud" is over-used, but a 48-core chip is certainly a good match for anyone who uses virtualization, and cloud-style data services are absolutely big users of virtualization.
Cloud computing is certainly a big deal. I recently explained to my boss that instead of spending weeks going through tickets, bureaucracy, approvals, and procurement to get a server in our own datacenter, we could go to Amazon, type the credit card number, and be up-and-running with a few clicks!
I don't know if he understood
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Why is everything called cloud these days? Yet another du jour buzzword. Is this really justified here?
Given that making effective use of these cores would call for engineering code to work with any number of cores, as opposed to just 2, 4, or 8, then yes it is semi-justified, especially if aimed at the server market. I do say 'semi', though, because I partially agree with you about its silliness.
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http://en.wikipedia.org/wiki/File:Cloud_computing_types.svg [wikipedia.org]
Now imagine you'd have this 'cloud CPU' as your server at home that runs apps that you could acces with Google Chrome OS... Great family server... Or remote X and play Doom3 at work from your netbook.
Sounds interesting now? ;)
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They're Intel... they have this buzzword department, and those kiddies have to make a living, too. Remember the Intel Pentium 4 "Netburst" architecture. Nothing whatsoever to do with nets, networking, the internet, etc.... other than the fact Intel Marketroids were trying to convince all the Mundanes (Muggles, to you kiddies) that this CPU would magically make their internet go faster. Yup, that's it.. not the fact you're on a frickin' POTS modem.
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Only 48? (Score:5, Funny)
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Obligatory (Score:2)
Imagine a Beowulf Cluster of These !!
Obligatory "Fixed that for you" (Score:3, Funny)
There, fixed that for you.
Great cost savings (Score:5, Funny)
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This is an Intel chip we are talking about here... you can just round off that result ;)
Synergy! (Score:5, Funny)
This new Cloud processor should create synergies with my SOA Portal system and allow me to deploy Enterprise B2B Push based Web 2.0 technologies!
Is there enugh cpu to chipset bandwith to make use (Score:5, Interesting)
Is there enough cpu to chipset bandwidth to make use of all this cpu power?
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If you need very little data per core but are executing sick calculations, then yes. But probably not anything realistic...
Re:Is there enugh cpu to chipset bandwith to make (Score:4, Interesting)
Is there enough cpu to chipset bandwidth to make use of all this cpu power?
That's really going to depend on the intended use. And on whether the intended use involves problems that a) can be efficiently parallelized, and more importantly, b) actually have been efficiently parallelized. But unless each core gets its own memory bus and its own dedicated memory with its own cache, I rather expect that the only things that are going to be parallelized to their maximum potential are wait states. All that said, it will still probably run faster than a two- or four-core CPU for many tasks, but it won't be running 48 times faster. I would not, however, refuse a manufacturer's sample if one was handed to me. ;)
On the positive side, if this beast actually makes it to market, it might help spur the development of new parallel software.
Sun HAS a 64 thread processor: UltraSPARC T2 (Score:4, Informative)
More info at:
http://www.sun.com/processors/UltraSPARC-T2/specs.xml [sun.com]
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All intel has to do is re implement Hyper Threading in each core.
48 cores = 96 threads, IIRC.
Not the same thing (Score:4, Informative)
Sun's processors are heavily multi-threaded per core. It is an 8 core CPU where each core can handle 8 threads in hardware. Intel's solution is 48 separate cores, doesn't say how many threads per core.
The difference? Well lots of threads on one core leads to that core being well used. Ideally, you can have it such that all its execution units are always full, it is working to 100% capacity. However it leads to slower execution per thread, since the threads are sharing a core and competing for resources.
Something like Sun's solution would be good for servers, if you have a lot of processes and you want to avoid the context switching penalty you get form going back and forth, but no process really uses all that much power. Web servers with lots of scripts and DB access and such would probably benefit from it quite a lot.
However it wouldn't be so useful for a program that tosses out multiple threads to get more power. Like say you have a 3D rendering engine and it has 4 rendering threads. If all those threads got assigned to one core, well it would run little faster than a single thread running on that core. What you want is each thread on its own core to give you, ideally, a 4x speed increase over a single thread.
So in general, with Intel's chips you see not a lot of thread per core. 1 and 2 are all they've had so far (P4s and Core i7s are 2 threads per core, Core 2s are 1 thread per core). They also have features such as the ability for a single core to boost its clock speed if the others are not being used much, to get more performance for one thread and still stay in the thermal spec. These are generally desktop or workstation oriented features. You aren't necessarily running many different apps that need power, you are running one or maybe two apps that need power.
As for this, well I don't know what they are targeting, or how many threads/core it supports.
Sounds like Sinclair's waffer scale intergration. (Score:2)
It does sound a lot like it. Truth is that it is probably a lot more like the old Pentium D packages but still kind of interesting.
So how many Coretex A8 cores could you fit on one of these?
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The 48-core chip that Intel demonstrated is 45nm!
Also, Cortex-A9: "For 2000 DMIPS of performance when designed in a TSMC 65 nanometer (nm) generic process the core logic costs less than 1.5 mm^2 of silicon." ( http://www.arm.com/products/CPUs/ARMCortex-A9SingleCore.html [arm.com] ) So it seems "up to 3 mm^2" in your quote really means "up to" (and for a much older core of course, when it was just launching 4 years ago)
And Cortex-A9 "consumes less than 250mW per core"...
Re:Code Name is Offensive (Score:5, Insightful)
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I thought a bangalore was a man portable explosive, telescoping lance used to take out pill boxes in WW2?
Re:Code Name is Offensive (Score:5, Funny)
That was an offshoot technology. They've finally got all the bugs ironed out and the CPU is much less prone to "uncontrolled exothermic reactions" then it use to be.
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Oh please don't go over your head in this.
India's tech field has improved, but not to the point of design such a chip yet !
Without the West, India is still a big nothing !
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Without the West, India is still a big nothing !
And vice versa :p
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In this position, you will be responsible for architecting advanced client platforms for 2015 and beyond. We are now in the early research and pathfinding for the 2015 generation of CPU products. Our team engages in early architecture analysis, microarchitecture research and/or development, performance and/or power modeling and analysis, including detailed architecture validation versus RTL
Here's what they do in Bangalore: http://www.intel.com/jobs/india/iidc/index.htm [intel.com]. Seems like some people in India have enough skills to design a CPU.
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As in The Big Bang Theory season 3 episode 4: "I don't want to go to India. It's hot and loud and there's so many people. You have no idea, they're everywhere."
Re:Code Name is Offensive (Score:4, Funny)
Intel an American company, with the American economy in the shape it's in, I am offended at the codename Bangalore.
As the last remaining operational Soong type android, I am offended by the name Bang-A-Lore.
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Intel an American company, with the American economy in the shape it's in, I am offended at the codename Bangalore.
As the last remaining operational Soong type android, I am offended by the name Bang-A-Lore.
So you're B4, then?
Well, I guess it was several years ago that you were known as B4... What's the name you're using these days... "Pryor", isn't it?
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Does the fact that none* of the Apple Operating system names are of animals not native to America?
*After 5.1, which is "Kodiak" - which can be found in Alaska.
5.2 Mac OS X v10.0 "Cheetah"
5.3 Mac OS X v10.1 "Puma"
5.4 Mac OS X v10.2 "Jaguar"
5.5 Mac OS X v10.3 "Panther"
5.6 Mac OS X v10.4 "Tiger"
5.7 Mac OS X v10.5 "Leopard"
5.8 Mac OS X v10.6 "Snow Leopard
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there are pumas in the American west and in Florida, they are just called Mountain Lions or Cougars or Floida Panthers. same thing.
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I refuse to call a Mountain Lion a Puma.
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I refuse to call a Mountain Lion a Puma.
Just don't call a Warthog a Puma. Sarge doesn't like that.
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True. We don't have many BIG cats in the U.S. ... just a lot of FAT cats (greater concentrations can be found in the vicinity of State Capitols and Washington D.C.).
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How awful of them to use the name of San Fransisco's sister city, the "Silicon Valley" of India, as a product codename. Were you equally offended when Ibex Peak, Tylersburg, Alviso, Calistoga, Lakeport, Broadwater, Eaglelake, Crestline and Cantiga were used as codenames?
You don't need to get your panties in a twist over this. Although it is worth mentioning that it makes you look like a racist when you assume that an innocuous naming decision is some form of racial bigotry or social commentary.
Re:Code Name is Offensive (Score:5, Funny)
> This post is copyrighted by Robert Nelson for the private use of his audience. Any other use of this post or of any pict
Your sigfile is offensive. What have ye got against the Scots?
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What have ye got against the Scots?
Damn Scots!
They ruined Scotland!
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Damn Scots! They ruined Scotland!
Scotland? What is that? All I know of is Pictland.
Mummy? (Score:3, Funny)
Insightful WTF? If you get offended that easily, you'd better:
Mummy?
Are you my mummy?
Mummm-myyy...
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Re:Windows 12 (Score:5, Interesting)
Microsoft once had a podcast where they were talking about multi-core CPU kernels. Their belief was that once you had 50+ cores, you would be able to have a mutex for every single COM object element, simply because you could.
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my idea when you had enough was that each process thread can be on it's own processor, is the idea of a mutex for every com object similar? I don't really get 100% what a mutex is.
Re:Windows 12 (Score:5, Informative)
It is most often required because resources are normally not 'atomic.' For instance, a string in memory is made up of many machine words and a CPU cannot read or write multiple machine word values in one operation. The danger is that while one CPU is writing to such a non-atomic collection of values, another might be trying to read from (or write to) it.. creating a situation where that second process reads part of the old data and part of the new data (essentially garbage data.)
So the idea of a MUTEX is born, in which an atomic value is leveraged to allow a thread to reserve such resources, signaling others (if they respect the MUTEX as well) to wait their turn.
Re:Windows 12 (Score:4, Informative)
It doesn't matter much. The first sibling to grab key 1a is usually running for the car. Even if the other sibling grabbed key 1b, they'll be looking at an empty parking spot, complaining to mom. :)
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Just imagine.. a Beowulf cluster^2!
Re:Codenames (Score:4, Funny)
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There, fixed that for you.
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Re:Codenames (Score:5, Informative)
Why can companies not come up with decent code names. For instance, this would be the perfect case for it being codenamed "Beowulf".
They're using geographical names (cities, places, lakes, rivers) to avoid having to register the codename as a trademark. Geographical names can't be trademarked so no one will use your codename for his trademark.
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> They called it Bangalore because they are going to farm out your processes.
To Maine..??
(Oh, sorry, that's Bangor. My bad!)
Uh, no. That's Bang-ah, Maine. Bangor is a Myth.
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Re:So ... (Score:4, Informative)
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All of them except windows.
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What? Vector units inside?
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Leaked? Dude I got the freaking instruction set in my mailbox. Want the public PDF? It's an ordinary x86-64 CPU that is capable of vector processing stuff...
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At about 20-30 fps, according to Intel, with Pixomatic 3 :')
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