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MIT's Hybrid Microchip To Overcome Silicon Size Barrier 77

schliz writes "MIT researchers have successfully embedded a gallium nitride layer onto silicon to create a hybrid microchip. The method could be further developed to combine other technologies such as spintronics and optoelectronics on a silicon chip. It is expected to be commercialized in a couple of years, and allow manufacturers to keep up with Moore's Law despite today's shrinking devices."
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MIT's Hybrid Microchip To Overcome Silicon Size Ba

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  • by imgod2u (812837) on Monday September 21, 2009 @11:37AM (#29492019) Homepage

    They aren't talking about shrinking existing MOS transistors (which make up 99.999% of digital circuits); which is what Moore's Law talks about. They're talking about the ability to integrate transistors with better matching characteristics (CMOS is terrible at it) for analog and photoelectric circuits onto existing silicon. This idea has been done again and again from Intel's hybrid silicon laser to Silicon Germanium, which is already widely used in cell phone chips.

    This won't make digital circuits smaller and isn't a solution to it so the headline isn't accurate. What this will mean is that potentially, cell phones won't need 4-5 separate chips for RF, digital, baseband, etc. You can integrate all those functions into one. But again, that's nothing new. IBM already provides BiCMOS with a SiGe layer on top for analog circuits. It's not been economical since it usually lags behind their bulk CMOS process for digital-only chips.

  • by imgod2u (812837) on Monday September 21, 2009 @12:32PM (#29492753) Homepage

    You're talking about coupling capacitance, which is something that can be alleviated by design. The biggest issue is that shrinking wires don't result in faster signals due to the load capacitance remaining relatively the same. This becomes the majority of the delay and the speed of the transistor becomes a smaller part of the equation.

    Add to this the fact that transistors themselves aren't getting faster. The speed of a FET is proportional to its gate dielectric thickness. That is 1nm at 45nm and 0.9nm at 32 (for Intel). This can't really shrink much more like it has in the past -- once you're down to a single layer of Hafnium, you can't really cut out any more -- and as a consequence, transistors won't be getting faster at the same rate that they have been in the past (for MOS at least).

    Looking at Intel's roadmap, upcoming node shrinks scale in power and size but not in speed.

  • by treeves (963993) on Monday September 21, 2009 @04:17PM (#29495917) Homepage Journal
    You don't make the case out of CNTs. You put them in the plastic to make it (much) stronger. A composite material. The carbon fibers needn't be "nano" to work well though.

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