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The Father of Multi-Core Chips Talks Shop 90

Posted by timothy
from the green-onion-layered-beneath-yogurt dept.
pacopico writes "Stanford professor Kunle Olukotun designed the first mainstream multi-core chip, crafting what would become Sun Microsystems's Niagra product. Now, he's heading up Stanford's Pervasive Parallelism Lab where researchers are looking at 100s of core systems that might power robots, 3-D virtual worlds and insanely big server applications. The Register just interviewed Olukotun about this work and the future of multi-core chips. Weird and interesting stuff."
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The Father of Multi-Core Chips Talks Shop

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  • by Wesley Felter (138342) <wesley@felter.org> on Saturday July 19, 2008 @06:47PM (#24257037) Homepage

    For servers, POWER4 was released in 2001. For desktops, the Pentium D came out in mid 2005 and the PowerPC 970MP a few months later. All of these came out before Niagara.

  • by TheRaven64 (641858) on Saturday July 19, 2008 @07:05PM (#24257181) Journal
    Read more carefully. He created the Stanford Hydra in 1994, and the Niagara is based on this design. They are not claiming the Niagara was first.
  • by cnettel (836611) on Saturday July 19, 2008 @07:05PM (#24257183)
    Those processors have all been part of maintaining the illusion of the von Neumann machine, and to maintain common interfaces between different pieces of hardware. What's happening now is that the model of a single instruction feed is breaking down completely, no matter what task you want to do, if you want it done efficiently. And that's for the very reason that the very smart people designing chips have run out of ideas on how to make them faster while maintaining that very convenient illusion for the smart people writing software for those chips.

    No one wants to write threaded code for computations, if it can be done serially. (Parallelism can be quite convenient for processing of requests, like a server, but even then most designs unless done with great care will contain synchronization or non-locality in one way or another.)

  • by yumyum (168683) on Saturday July 19, 2008 @07:55PM (#24257489)

    I just finished taking a course at MIT on multiprocessor programming. It was taught by the authors of The Art of Multiprocessor Programming [elsevier.com], Maurice Herlihy and Nir Shavit. I highly recommend their book, their classes, their expertise. They are now focused on transactional memory, which may make things a bit easier to program in the multiprocessor universe. Of course we can stick with course-grained locking, but as they pointed out early on, Amdahl's Law [wikipedia.org] shows that throwing hardware at a problem may not be successful in upping performance by the amount you expect if the system's scheduler has no hopes of keeping the cores busy due to how you've written your code.

  • Re:Well (Score:3, Informative)

    by maeka (518272) on Saturday July 19, 2008 @08:17PM (#24257627) Journal

    Multicores in the average PC is just marketing.

    I'm sorry you do not have a need to run more than one CPU intensive process at a time.

    The laptop I am typing this on is 8 years old 2.2GHz celeron

    You are significantly [wikipedia.org] off on your estimate of its age.

  • Re:Horse Pucky..... (Score:1, Informative)

    by Anonymous Coward on Saturday July 19, 2008 @11:50PM (#24259143)

    Mainframes use 386 chips for I/O controllers and even those sit there and loaf, talk about a waste of electricity! About .01% of the worlds computers need the kind of power that a CPU with more then say 4 cores provide. Those that do are rather busy doing insanely complex mathematics, but even then I doubt that the CPU(s), even when running at "100%" utilization are actually doing the work that they were programmed to do, rather they are waiting for I/O to a database or RAM and fetching data.

    IBM mainframes use PPC 440 processors in their channel cards. You are wrong. PPC 440 is not fast enough. Look at their pathetic Ficon IOs/sec numbers vs. an Emulex FCP adapter.

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