Scientists Pave Way For 25nm CPUs

arcticstoat writes in with word that scientists at the Space Nanotechnology Laboratory at MIT have found a new way of extending Moore's law into the future — they have succeeded in etching a grid of 25nm lines into a silicon wafer. The article notes that this technique could be used for writing the grid on which chips are laid down, but that the electronic elements would have to be written using more complex techniques. "[Researchers] created an interference pattern using light from a laser with a wavelength of 351 nm. The pattern consists of alternating light and dark zones repeating every 200 nm. This allowed them to etch 25-nm lines into a silicon wafer, each 175 nm apart. They then repeated the process three times, each time shifting the interference pattern by 50 nm and etching another 25-nm groove. The resulting grid has alternating 25-nm stripes and grooves..."

This is a bad headline title.

[RightSaidFred99]

25nm is nothing to write home about, companies are already planning for 25nm. What's exciting is that they created a feature that was smaller than the wavelength of the light used to etch it. Had they used 400nm light to create a 45nm feature, would the title have been "MIT breakthrough could lead to 45nm chips!!!"?

ASML has roadmap upto 16 nm chips,

[Anonymous Coward]

ASML already has working tools for 32 nm litho. 16 nm is planned in next couple of years.
http://www.asml.com

Re:wow - 25nm

[omeomi]

I'm still trying to figure out what the heck "scientists at the Space Nanotechnology Laboratory at MIT " is?? Are they like...A small lab on the space station??? Huh?

er, MIT is a school in Massachusettes. They have a laboratory called the Space Nanotechnology Lab [mit.edu].

Shrinking in size is one part of the problem

[feranick]

The process of making smaller features is only a small fraction of the problem in producing 25nm (or smaller) Si-based electronics. Left aside quantum effects, which start to dominate at length scales smaller than 10nm, stability and electrical leakage through the gate are the most significant problems. When Intel went from 65nm to 45 nm, it wasn't just a "shrinking" process, but an all new use of materials design had to be used to deal with the gate current leakage. In simple words, the silicon oxide insulator was just too thin not to leak. The new metal high-K (Hafnium-based) is the major step that allowed those chip to be made. This research is good, but it solves only a small fraction of the difficulties the electronics industry faces in dealing with Moore's law.

linewidth != wavelength

[tsjaikdus]

You can create much smaller lines than the wavelength of your light. You use tricks for that, but that's how it is done at Samsung, IBM, Intel, etc. for ages.

Re:This is a bad headline title.

[damouloud]

Well, the fact that they've been creating features smaller than the wavelength of the illuminating light is nothing to write home about either.

Current chips (since at least the 180nm node) are being fabbed this way at all microelectronics fabs all around the world. We already use 193nm light to create features as small as 22nm (using tricks like immersion, double-exposure and OPC)

This doesn't impress me at all

[Cutie Pi]

First, IAALE (I am a lithography engineer) working on Intel's 22nm process technology. Let's clear up a few misconceptions:

1) The name of a logic node is directly related to the size of the features being made. Those names (e.g. 65nm, 45m, 32nm, etc.) used to relate to the "half-pitch" of the minimum pitch that was printed. But that is not true today. 65nm used a minimum pitch of ~200nm, 45nm used ~140nm and 32nm is using ~100nm. The next node, 22nm is slated to use minimum a pitch of 72nm. The features discussed in this article have a pitch of 50nm, which would be equivalent to the node after 22nm, i.e. 16nm.

2) It's not hard to print features smaller than the wavelength of light. For the lens based systems we used, the Rayleigh criterion gives the minimum pitch possible: 0.25*lambda/NA, where lambda=wavelength (193nm) and NA=numerical aperature (1.35 for the best lenses). So 72nm is the minimum pitch, already much smaller than the wavelength

3) I hate to break it to these researchers, but interferometry has been used for a looong time to make gratings. Search for "interferomety lithography" on Google Scholar. The fourth link is called "Nanolithography using extreme ultraviolet lithography interferometry: 19 nm lines and spaces". That paper is from 1999. And they did that one exposure, not three (using a smaller wavelength).
You would actually need at least one more exposure to divide the grating into something that resembled a logic circuit. The technique in this artcle is not practcal for a number of reasons, but we can do better than them using pitch-doubling techniques and only two exposures.

Re:Is the gap closing?

[Anonymous Coward]

Both Xilinx and Altera are fabless so their time to market depends on their ability to execute given the process parameters or cell libraries supplied by the foundry of their choice.