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Supercomputing IBM Hardware Technology

IBM Water-Cools 3D Multi-Core Chip Stacks 170

An anonymous reader writes "Water cooling will enable multi-core processors to be stacked into 3D cubes, according to IBM's Zurich Research Laboratory which is demonstrating three-dimensional chip stacks. By stacking memory chips between processor cores IBM plans to multiply interconnections by 100 times while reducing their feature size tenfold. To cool the stack at a rate of 180 watts per layer, water flows down 50-micron channels between the stacked chips. Earlier this year, the same group described a copper-plate water cooling method for IBM's Hydro-Cluster supercomputer. The Zurich team predicts high-end IBM multicore computers will migrate from the copper-plate water-cooling-method to the 3-D chip-stack in five to 10 years." Reader Lilith's Heart-shape adds a link to the BBC's article on these internally-cooled chips.
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IBM Water-Cools 3D Multi-Core Chip Stacks

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  • Electrolysis (Score:5, Interesting)

    by mrbluze ( 1034940 ) on Friday June 06, 2008 @10:45AM (#23682011) Journal

    To cool the stack at a rate of 180 watts per layer, water flows down 50-micron channels between the stacked chips.
    I wonder what reactivity of water with the surrounding surfaces will do to the life of the chip. AFAIK pretty much anything that uses water has an inherent limitation to its life, owing to the presence of superoxide radicals and free hydrogen ions.
  • 3D CPU structure (Score:3, Interesting)

    by Lord Lode ( 1290856 ) on Friday June 06, 2008 @10:51AM (#23682087)
    I always liked the idea of a 3D CPU with all the cores and memory interweaved through each other in a way to have the optimal short path for its purposes. A LOT of memory could be there right next to the CPU. It would be fast even without clocking it very high, so not even have to consume that much watts per layer. It's a crazy amount of watts per layer mentioned in the article btw...
  • by Yetihehe ( 971185 ) on Friday June 06, 2008 @12:01PM (#23683059)

    How long will it be before my computer heats my house while I browse the internet? When does the first combined datacenter and heating cogeneration system get installed?
    About two months ago. http://www.ecofriend.org/entry/ibm-manages-to-warm-pool-water-with-its-heat-emissions/ [ecofriend.org]
  • by Sandbags ( 964742 ) on Friday June 06, 2008 @01:07PM (#23684023) Journal
    Much more importantly, 50 micron tubes will be extremely fragile. To move water in sufficient quantity to avoid such small samples reacking critical temps while inside the CPU is going to be REALLY difficut. with tubes only a few mollocules in diameter, extremely consistent pressure will need to be maintained. A bubble forming due to boiling would shatter the substructure of the CPU and destroy it. Too high pressure and pipes burst. Too low pressure, and water won't move fast enough to avoid either boiling and ruptuing the core, or in causing the CPU to overheat internally.

    A good idea? possibly. Practical in a production environment? not likely.

    As you said, any contaminant of any kind would destroy the systenm as well. at the micro-pressures involved in a safe system, it's unlikely they'll be appropriate pressures to involve a water filter...
  • by necro81 ( 917438 ) on Friday June 06, 2008 @01:51PM (#23684649) Journal
    CMOS is still a whole lot more power efficient than the TTL logic (i.e., bipolar junction transistors) that they replaced. Ideally, a CMOS transistor only requires power when switching states, whereas a BJT burns power continuously. Per transistor, they are a much better way to go.

    The problem with high total power dissipation is the result of several interrelated trends, all of which can be related to Moore's Law. More transistors got crammed onto a single chip (a linear increase in power dissipation - double the transistors doubles the power). The clock speeds increased from kHz to MHz to GHz (power increases linearly (or squared) with increasing frequency). Thinner gate oxides permitted greater leakage currents. These trends can also be weighed against competing trends that save power, the greatest being that a smaller transistor uses less power than a large one - it is proportional to area.

    The result is that you have orders of magnitude more transistors in a chip (hundreds of millions for a microprocessor), switching orders of magnitude faster (a few GHz), while each transistor is orders of magnitude smaller (less than a square micron) and requires orders of magnitude less power per switch.

    On balance, it means that a microprocessor's TPD has increased only 1-2 orders of magnitude over the last few decades, and has leveled out at ~100 W as a sort of practical limit. When you think about it, and consider that a microprocessor today is millions or billions of times more computationally powerful than the first CPUs, it is amazing that all these orders of magnitude manage to balance out to a reasonable increase.
  • by jank1887 ( 815982 ) on Friday June 06, 2008 @02:07PM (#23684863)
    helium doesn't cool things to low temps. you cool the helium down to low temps, and then pump the cooled helium against your heat source. it takes a lot of energy to cool the helium in the first place, and would take up a lot of space.

Intel CPUs are not defective, they just act that way. -- Henry Spencer

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