AMD Announces Triple-Core Phenom Processors 334
MojoKid writes "AMD has officially announced their triple-core Phenom multi-core processor offering, suggesting a triple-threat of processors, from dual-cores to triple-cores and native quad-cores coming to market this year. While the term symmetric multi-processing (or SMP) suggests a balanced approach of multiple cores in an even number of engines working together on a single workload, AMD offers that an odd number of processors can slice at that workload just as efficiently. Time will tell how this architecture will scale amongst various multi-threaded applications and real-world usage models. AMD is definitely moving to make use of these quad-cores that don't quite make the cut by testing them fully as triple-cores and realizing some revenue, rather than throwing them away."
Nothing new here. (Score:5, Informative)
Why Yes. Yes it does. From HERE [wikipedia.org]:
Someone has been brainswashed (Score:5, Informative)
It's about multiple cores processing simultaneously. Check the article I link to, even the damn example diagram has 3 cpu-s.
Just a binned part? (Score:4, Informative)
And why should ``symmetric'' imply even? It merely implies that all cores see memory with the same class of service. And, in reality, aren't most AMD multiprocessors cc-NUMA machines, not SMP?
For most workloads, if they are fairly multithreadable, 3 processors available will be just fine. I know of very few workloads that require an even number of processors, and even if it were the case that the task were split into an even number of threads, the OS should have no problem scheduling on a reduced number of processors.
Hey, doesn't the XBox 360 have a 3-core PPC in it?
Even? What the hell? (Score:4, Informative)
Re:Someone has been brainswashed (Score:5, Informative)
However, AMD is definitely moving to make use of these quad-cores that don't quite make the cut, by testing them fully as triple-cores and realizing some revenue, rather than throwing them away.
The triple-core Phenom is an actual Phenom architecture, it's not 4-core rejects. Jesus Christ, NEVER accept submissions from hothardware.com anymore!
That's the worst one in months.
SMP Doesn't Suggest Even Numbers Of Processors (Score:5, Informative)
SMP refers to the fact that all the processors are identical and share the same memory (in contrast to NUMA designs like multi-chip Opteron systems). However, I've seen more and more people refering to cache coherent NUMA designs like multi-core opteron and the upcoming CSI based intel systems as SMP systems which, while a stretch of the definition, is at least reasonable.
Suggesting that SMP has anything to do with having an even number of processors is just DUMB. It may be the case that SMP systems usually have an even number of cores (I don't know) but that's not what the writeup or article seem to be saying.
Re:Just a binned part? (Score:5, Informative)
This is what the article authors suggest, but no, it's a separate architecture. While I suspect it's possible a subset of the 4-core Phenoms to be relabelled as 3-core Phenoms, the bulk of 3-core Phenoms will be built as 3-core parts from the very start.
And, to add insult to injury, this is a quad-core Phenom on the picture, since it's all the authors of the fine article could find. In other words, they are idiots.
Re:2^n = 3, where n belongs to Z is not possible (Score:4, Informative)
Supposedly 3 core is actually pretty nice in some ways, as each core has a direct link to the other two. On a quad core system, each core is linked to two others, so sometimes it takes two hops to get messages from one core to other, slowing things down.
Re:Symmentric connections? I think not (Score:3, Informative)
Re:2^n = 3, where n belongs to Z is not possible (Score:3, Informative)
Re:Someone has been brainswashed (Score:4, Informative)
Re:Someone has been brainswashed (Score:1, Informative)
It was used in a couple different Honda cars... (Score:3, Informative)
Next question please...
Re:I wonder how many GHz these can crank out (Score:3, Informative)
Re:For the cleanest, most comfortable shave ever! (Score:5, Informative)
Re:Symmentric connections? I think not (Score:2, Informative)
AMD's multi-core processors use a fully-connected crossbar switch in the on-die northbridge to communicate. There is only one "hop" between each core.
What you're thinking of is a four-socket system whose interconnect network is not fully-connected - it's only the edges of a square, and there are two missing links between the "corners" of the square. That is certainly a legitimate topology for a four-socket system, with the limitation you pointed out (two hops to get to the opposite node), but it doesn't apply to AMD's quad-core die.
Re:Someone has been brainswashed (Score:5, Informative)
The symmetry in SMP does not refer to the capabilities of the processors. It refers to the relation between the processors and memory.
In symmetric multiprocessors, all processors access the same shared memory uniformly. That is, memory access delays depend neither on what memory zone nor from which processor it is being accessed.
In contrast, in NUMA architectures (non uniform memory access), each processor holds a portion of the shared memory that it can access very quickly. A processor can also access the portions of other processors but this incurs potentially large delays.
At the end of the spectrum, asymmetric multiprocessors combine processors with different capabilities. Here, asymmetric indeed most probably refers to the fact that processors are different. However, while most (all?) actual implementations using a NUMA architecture do use identical processors, they are never said to be symmetric because of the memory access.
Re:Single, double, triple, and quad (Score:5, Informative)
The idea of post-factory error detection isn't so far-fetched. If a chip passes QA, the sorts of defects you'll see later in its life are likely to be thermally induced, and the likelihood that the defect will manifest prior to loading of the BIOS is very low. You're not using the MMU or the FPU at all, you're not using much of the cache, you can be running at your minimum power setting, and you're not doing it long enough to heat up much. If a core gets marked bad due to an excess of MCEs, similar to how many systems can mark DIMMs bad on excessive multi-bit ECC errors, the BIOS simply doesn't need to bring it online at boot time. Even if core 0 is the faulty one, you can probably load just enough of the BIOS to bring a good core online and finish booting, since you're not straining it enough to cause thermal problems, and you're only using a tiny fraction of the instruction set and die transistors. This sort of High Availability feature probably won't make it to the desktop right away, but as core counts keep increasing, it's inevitable.
Re:A very real reason for using triple-core (Score:5, Informative)
Firstly, for any general multi-node graph, it's entirely possible for three, four, eight, or any number of nodes to be only one hop away from each other. See fully-connected mesh [wikipedia.org]. For the four-node case, imagine a 2D square, connected on the four sides, plus two links connecting the "diagonals" of the square. In that topology, each of the four nodes are only one hop away from each other. Of course, as the number of nodes increases, the cost of fully connecting them increases, as does the processing cost to multiplex and process transactions into the node from the (n-1) incoming links, but with only four nodes it's entirely possible to create a fully-connected network.
Wiith AMD multi-core processors, all of the cores communicate using a fully-connected crossbar switch in the on-die northbridge - meaning all cores on the die are one "hop" away from each other, including the four-core case. What you're probably thinking of is a multi-socket system that only has two coherent links per socket - that would prevent you from making a fully-connected coherent interconnect for a 4-socket system.
Re:Someone has been brainswashed (Score:3, Informative)
Re:With apologies to the Onion (Score:5, Informative)
Mod parent up, please, and while you're doing that, read this:
http://www.theonion.com/content/node/33930 [theonion.com]
Re:Someone has been brainswashed (Score:4, Informative)
Wikipedia [wikipedia.org] would disagree with you: "Symmetric multiprocessing, or SMP, is a multiprocessor computer architecture where two or more identical processors are connected to a single shared main memory."
SMP implies that there is a shared memory address space and that the cores can execute similar binaries. NUMA implies separate banks of memory dedicated to specific CPUs -- for example, AMD Opteron. However, most vendors still call the Opteron 'SMP' when used in a multi-CPU configuration because the "independent" banks of memory are mapped into the same memory address space (visible from all CPUs) and there is neglible penalty for executing tasks on either core regardless or location of code or data ***. (*** note: memory banks shouldn't be completely ignored for memory intensive high-performance computing applications and indeed on certain OS's like Vista, it is possible to allocate memory with CPU affinity or to schedule tasks with CPU affinity on an Opteron to alleviate NUMA crosstalk between the CPUs).
ASymmetric MultiProcessing (ASMP) implies dissimilarity in either the processing units (different binary opcodes) or disjoint memory accesses. Using a physics-accelerator or a generic-GPU programming with a main CPU is asymmetric processing even if the accelerator can access the same memory as the CPU (i.e. from cheap "shared-memory" GPU such as those integrated on cheap motherboards or to more powerful ones such as the GPU in the XBOX360). The CELL in the PS3 is not SMP because the PPU and SPU can not execute the same binaries and the cores are asimilar even though all cores have some method of accessing the main memory with a shared address space (although the SPUs also use a DMA read/write to main memory rather than direct access which would doubly qualify them as ASMP - but even without this memory difference, they would still be ASMP processing).
Re:With apologies to the Onion (Score:3, Informative)
Re:A very real reason for using triple-core (Score:3, Informative)
We're talking about CPUs & AFAIK, the the traces can't cross one another..
Unless they commercialized some 3D process @ 65nm that I didn't read about. Wiith AMD multi-core processors, all of the cores communicate using a fully-connected crossbar switch in the on-die northbridge - meaning all cores on the die are one "hop" away from each other, including the four-core case. Sooo...
Cpu 1 --> hop --> northbridge --> hop --> CPU 4
Or am I misunderstanding the definition of a "hop"?
Not even that.. (Score:4, Informative)
All that said, SMP has nothing to do with an even number of processors/cores. It just means each processing element of a system is roughly equivalent. So you have a choice of three parts to schedule something on, the scheduler can know all three are equally capable and the heuristics for processor selection are straightforward. ASMP typically has specific roles for each part (i.e. a dedicated processor for interrupts, etc etc)
Re:With apologies to the Onion (Score:3, Informative)
No, the thing that's awesome is that eighteen months after the Onion article was published, Gillette actually did it [cnn.com].
Re:2^n = 3, where n belongs to Z is not possible (Score:4, Informative)
Another reason why powers of two are popular with multicore chips is that powers of two can be laid out into rectangles. If your multicore design is basically a copy-and-paste job with a little glue logic, it's a lot easier to lay out the cores. With something like the Cell, 8 is a nice number of cores since it allows you to have two rows of four. Three is just awkward.
The Cells found in the Playstation 3, however, did not have 8 SPU cores, they had 7. This is because most of the die space is the SPUs and you can dramatically increase yields if you only expect 7 of the 8 to work. If a single SPU has a manufacturing flaw, you just disable that one and sell pop the chip in a PS3. If none of them do, you sell it for more expensive blades.
AMD and Intel have been doing this for a while. Chips with flaws in the cache have some of the cache disabled and are sold more cheaply. In addition AMD chips are designed with three hypertransport controllers. If only one works, the chips are sold as Athlon 64s. If two work, they are cheap Opterons, if all three work, they are expensive Opterons (exactly how expensive depends on how many flaws there are in the cache area). Similarly, with the dual core lines flaws in one core result in them being marked down as single-core chips.
Intel, currently, sell quad core chips containing two separate dies. If either die has a flaw, it is sold as a Core Solo and not put in a dual-die package. AMD, however, are going to be making single-die quad-core chips. Selling three-core versions allows them to make use of the ones with a flaw in one core. This should help keep their yields high (and thus their costs relatively low), since it means that they can sell flawed chips almost irrespective of where the flaw is, just marking it down as a cheaper part.
Re:A very real reason for using triple-core (Score:3, Informative)
There are around 10 metal layers in a modern IC. Traces can certainly cross one another on different layers.
I see what you're saying...but you're counting a processor interface as a hop. How many hops are there between cores in an Intel system then? CPU 1 --> hop --> front side bus --> hop --> CPU 4? No one counts hops that way. Your definition of hop would be like me saying there are two hops from your computer to your router, one between your processor and your network card over the PCI bus, and one between the network card and the router over ethernet.
Re:A very real reason for using triple-core (Score:4, Informative)
Before you call me incorrect, please take 2 minutes to look at some lecture notes from an intro VLSI course:
http://www.cse.sc.edu/~jimdavis/Courses/2005-Fall%20CSCE%20613/CSCE613-Week10-Chapter-04-05.pdf [sc.edu]
You can clearly see on page 3 (slide 6) that metal1 and metal3 are directly on top of each other. As I stated in a different post, you're confusing metal layer/wire routing in an IC with entire logic devices (transistors/gates/flops). Let me repeat it again for you: metal layers in an IC can cross.