Follow Slashdot stories on Twitter

 



Forgot your password?
typodupeerror
AMD Hardware

AMD Announces Triple-Core Phenom Processors 334

Posted by Zonk
from the chips-that-don't-require-dipping dept.
MojoKid writes "AMD has officially announced their triple-core Phenom multi-core processor offering, suggesting a triple-threat of processors, from dual-cores to triple-cores and native quad-cores coming to market this year. While the term symmetric multi-processing (or SMP) suggests a balanced approach of multiple cores in an even number of engines working together on a single workload, AMD offers that an odd number of processors can slice at that workload just as efficiently. Time will tell how this architecture will scale amongst various multi-threaded applications and real-world usage models. AMD is definitely moving to make use of these quad-cores that don't quite make the cut by testing them fully as triple-cores and realizing some revenue, rather than throwing them away."
This discussion has been archived. No new comments can be posted.

AMD Announces Triple-Core Phenom Processors

Comments Filter:
  • by StefanJ (88986) on Monday September 17, 2007 @10:29PM (#20647077) Homepage Journal
    Damnit, I haven't even used up all the cartridges that came with my Intel Core Duo!
    • Re: (Score:2, Offtopic)

      by MikeFM (12491)
      I live in fear that they'll come out with a 16 core CPU before I get proper usage out of my two quad-core Xeon's. On the other hand I'd love to have dual 16 core Xeon's! :)

      Is it wrong that I'm thinking of building a water cooled laptop with 8 cores, a RAID5 with ~2TB of usable space, and a 24" monitor? I'm imaging a computer roughly the size of a large pizza box. Woot!
      • by sumdumass (711423)
        Who's lap is this freak show of a laptop supposed to fit in again?

        It isn't wrong unless you are thinking of taking it through airport security. In which case it would be hard to tell what could happen that wouldn't be expensive to you.
      • by AaronW (33736) on Tuesday September 18, 2007 @12:19AM (#20647863) Homepage
        I know of at least one 16-core [caviumnetworks.com] commercial processor. Oh, it runs Linux too.
      • Re: (Score:2, Funny)

        by SL Baur (19540)

        Is it wrong that I'm thinking of building a water cooled laptop with 8 cores, a RAID5 with ~2TB of usable space, and a 24" monitor?
        Probably. Can you imagine the amount of global warming a beowulf cluster of those things would cause? It might melt the polar icecaps instantly, but hey, that would solve the problem of the water cooling.
    • by Anonymous Coward on Tuesday September 18, 2007 @12:10AM (#20647799)
      Would someone tell me how this happened? Intel was the fucking vanguard of computing in this country. The Core Duo was the processor to own. Then the other guy came out with a three-core processor. Were we scared? Hell, no. Because we hit back with a little thing called the Core Trio. That's three cores and an fan. For cooling.

      But you know what happened next? Shut up, I'm telling you what happened -- the bastards went to four cores. Now we're standing around with our cocks in our hands, selling three cores and a fan. Cooling or no, suddenly we're the chumps.

      Well, fuck it. We're going to five cores.
      • by ejdmoo (193585) on Tuesday September 18, 2007 @02:48AM (#20648691)
        YES!!!!!!

        Mod parent up, please, and while you're doing that, read this:
        http://www.theonion.com/content/node/33930 [theonion.com]
      • Re: (Score:3, Interesting)

        by Tribbin (565963)
        But intel can't do 3-core by design right?
      • Re: (Score:3, Funny)

        by jollyreaper (513215)
        No, you missed a meme. Fixin' it for ya.

        Would someone tell me how this happened? Intel was the fucking vanguard of computing in this country. The Core Duo was the processor to own. Then the other guy came out with a three-core processor. Were we scared? Hell, no. Because we hit back with a little thing called the Core Trio. That's three cores and an fan. For cooling.

        But you know what happened next? Shut up, I'm telling you what happened -- the bastards went to four cores. Now we're standing around with our cocks in our hands, selling three cores and a fan. Cooling or no, suddenly we're the chumps.

        Well, fuck it. We're going to a beowulf cluster.

  • by Anne_Nonymous (313852) on Monday September 17, 2007 @10:30PM (#20647091) Homepage Journal
    I'm holding out for a processor that goes to 11.
  • Business as usual (Score:2, Insightful)

    by Daengbo (523424)
    Chip makers have been doing this for so long I can't actually remember when it started. Now it's cores, but it used to be cache. The chip doesn't pass QA, gets downclocked or rebranded for less cache and sold to the economy sector. Not earth-shattering news.
    • Re: (Score:3, Insightful)

      by mkosmo (768069) *
      Just like the Core Solo being defective Core Duos... so AMD is just following Intel's lead, once again! Then again, how could you blame them? It's good business. You don't have to scrap crappy chips that have at least semi-functioning cores. So you sell it as another product at minimal loss. I'm sure they still make money on it, so it keeps everybody happy: AMD and the economy consumer!
    • by adisakp (705706)
      FWIW, the Sony did this with the CELL processor on the PS3. Only 7 of the 8 SPU's are used to allow a higher yield. You can't use the 8th SPU even if it were functioning.
  • Nothing new here. (Score:5, Informative)

    by ArcherB (796902) * on Monday September 17, 2007 @10:34PM (#20647131) Journal
    Doesn't the XBox 360 have a triple core processor?

    Why Yes. Yes it does. From HERE [wikipedia.org]:

    Inside, the Xbox 360 uses the triple-core IBM designed Xenon as its CPU. While graphics processing is handled by the ATI Xenos which has 10 MB of embedded eDRAM, its main memory pool is 512 MB in size.
    • Re: (Score:3, Interesting)

      by n dot l (1099033)
      Sort of. Each core can run two threads at the same time (but both threads share the same cache, if I'm not mistaken) so it's somewhere between a hyper-threaded triple-core processor and 3 dual-core processors.
      • Re: (Score:2, Interesting)

        by Osty (16825)

        Sort of. Each core can run two threads at the same time (but both threads share the same cache, if I'm not mistaken) so it's somewhere between a hyper-threaded triple-core processor and 3 dual-core processors.

        It's still three cores on a single chip, and thus "triple-core". The architecture and functionality of an individual core doesn't matter, so long as it's capable of working as a single core (thus the PS3 is not an "8-core" or "7-core" system, since the Cell units are not functional as independent cor

  • by suv4x4 (956391) on Monday September 17, 2007 @10:34PM (#20647135)
    SMP [wikipedia.org] doesn't suggest the number of cores should be a power of two, it doesn't even suggest "even number of cores".

    It's about multiple cores processing simultaneously. Check the article I link to, even the damn example diagram has 3 cpu-s.
    • by suv4x4 (956391) on Monday September 17, 2007 @10:50PM (#20647261)
      Wait, I missed that, another lie:

      However, AMD is definitely moving to make use of these quad-cores that don't quite make the cut, by testing them fully as triple-cores and realizing some revenue, rather than throwing them away.

      The triple-core Phenom is an actual Phenom architecture, it's not 4-core rejects. Jesus Christ, NEVER accept submissions from hothardware.com anymore!

      That's the worst one in months.
      • by Phil-14 (1277)
        The triple-core Phenom is an actual Phenom architecture, it's not 4-core rejects. Jesus Christ, NEVER accept submissions from hothardware.com anymore!

        It's too late, the crowd here is already heading to a couple hundred snarky comments to "facts" that weren't facts to begin with.

        I'm assuming this chip would use the same style layout as the chip on the Xbox 360, but you probably won't find that sort of thing out here.
      • In theory with triple core, each processor is only 1 step away from the other processor (consider a triangular setup). With Quad core or greater there's either more bussing or more delays.

        Without seeing further details I sincerely doubt that these are quad-core chips with one dud core. I suspect AMD has actually used their technical brains here and given us the fastest non-(overly)complex multi core setup.

        Of course, if it's the bean counters in charge, then it's possible it's a failed quad core (though I s
        • by AcidPenguin9873 (911493) on Tuesday September 18, 2007 @02:12AM (#20648475)

          In theory with triple core, each processor is only 1 step away from the other processor (consider a triangular setup). With Quad core or greater there's either more bussing or more delays.

          Firstly, for any general multi-node graph, it's entirely possible for three, four, eight, or any number of nodes to be only one hop away from each other. See fully-connected mesh [wikipedia.org]. For the four-node case, imagine a 2D square, connected on the four sides, plus two links connecting the "diagonals" of the square. In that topology, each of the four nodes are only one hop away from each other. Of course, as the number of nodes increases, the cost of fully connecting them increases, as does the processing cost to multiplex and process transactions into the node from the (n-1) incoming links, but with only four nodes it's entirely possible to create a fully-connected network.

          Wiith AMD multi-core processors, all of the cores communicate using a fully-connected crossbar switch in the on-die northbridge - meaning all cores on the die are one "hop" away from each other, including the four-core case. What you're probably thinking of is a multi-socket system that only has two coherent links per socket - that would prevent you from making a fully-connected coherent interconnect for a 4-socket system.

          • Re: (Score:3, Informative)

            by TubeSteak (669689)

            Firstly, for any general multi-node graph, it's entirely possible for three, four, eight, or any number of nodes to be only one hop away from each other.

            Firstly, we're not talking about any general multi-node graph.
            We're talking about CPUs & AFAIK, the the traces can't cross one another..
            Unless they commercialized some 3D process @ 65nm that I didn't read about. Wiith AMD multi-core processors, all of the cores communicate using a fully-connected crossbar switch in the on-die northbridge - meaning all cores on the die are one "hop" away from each other, including the four-core case. Sooo...
            Cpu 1 --> hop --> northbridge --> hop --> CPU 4
            Or a

            • Re: (Score:3, Informative)

              We're talking about CPUs & AFAIK, the the traces can't cross one another.

              There are around 10 metal layers in a modern IC. Traces can certainly cross one another on different layers.

              Cpu 1 --> hop --> northbridge --> hop --> CPU 4 Or am I misunderstanding the definition of a "hop"?

              I see what you're saying...but you're counting a processor interface as a hop. How many hops are there between cores in an Intel system then? CPU 1 --> hop --> front side bus --> hop --> CPU 4? No one counts hops that way. Your definition of hop would be like me saying there are two hops from your computer to your router, one between your processor and your network card over the

    • by Frogbert (589961)
      Hold on, wouldn't you need an even number to denote symmetry?
      • by RedWizzard (192002) on Monday September 17, 2007 @11:42PM (#20647621)
        The symmetry in SMP has nothing to do with the number of processors. It simply means that all the processors are treated identically (and therefore should be identical in terms of capabilities). With asymmetric multiprocessing certain processors are used for certain tasks and are therefore often specialised for them.
        • by defago (314293) on Tuesday September 18, 2007 @12:38AM (#20647977)
          This is almost that, but still off the mark.

          The symmetry in SMP does not refer to the capabilities of the processors. It refers to the relation between the processors and memory.

          In symmetric multiprocessors, all processors access the same shared memory uniformly. That is, memory access delays depend neither on what memory zone nor from which processor it is being accessed.

          In contrast, in NUMA architectures (non uniform memory access), each processor holds a portion of the shared memory that it can access very quickly. A processor can also access the portions of other processors but this incurs potentially large delays.

          At the end of the spectrum, asymmetric multiprocessors combine processors with different capabilities. Here, asymmetric indeed most probably refers to the fact that processors are different. However, while most (all?) actual implementations using a NUMA architecture do use identical processors, they are never said to be symmetric because of the memory access.

          • Re: (Score:3, Informative)

            by RedWizzard (192002)

            The symmetry in SMP does not refer to the capabilities of the processors. It refers to the relation between the processors and memory.

            The symmetry refers to all the capabilities of the processors, including their access to memory. SMP means that all processors in the system are interchangable from the OS's point of view - that cannot be the case if any characteristic varies between the processors. A system with different processors that have the same access to memory (such as an unexpanded Amiga 1000) is not considered an SMP system.

          • by Carewolf (581105)
            In symmetric multiprocessors, all processors access the same shared memory uniformly. That is, memory access delays depend neither on what memory zone nor from which processor it is being accessed.
            No, that just crappy Intel SMP. Not true for SMP in general.
          • by adisakp (705706) on Tuesday September 18, 2007 @03:22AM (#20648863) Journal
            The symmetry in SMP does not refer to the capabilities of the processors. It refers to the relation between the processors and memory.

            Wikipedia [wikipedia.org] would disagree with you: "Symmetric multiprocessing, or SMP, is a multiprocessor computer architecture where two or more identical processors are connected to a single shared main memory."

            SMP implies that there is a shared memory address space and that the cores can execute similar binaries. NUMA implies separate banks of memory dedicated to specific CPUs -- for example, AMD Opteron. However, most vendors still call the Opteron 'SMP' when used in a multi-CPU configuration because the "independent" banks of memory are mapped into the same memory address space (visible from all CPUs) and there is neglible penalty for executing tasks on either core regardless or location of code or data ***. (*** note: memory banks shouldn't be completely ignored for memory intensive high-performance computing applications and indeed on certain OS's like Vista, it is possible to allocate memory with CPU affinity or to schedule tasks with CPU affinity on an Opteron to alleviate NUMA crosstalk between the CPUs).

            ASymmetric MultiProcessing (ASMP) implies dissimilarity in either the processing units (different binary opcodes) or disjoint memory accesses. Using a physics-accelerator or a generic-GPU programming with a main CPU is asymmetric processing even if the accelerator can access the same memory as the CPU (i.e. from cheap "shared-memory" GPU such as those integrated on cheap motherboards or to more powerful ones such as the GPU in the XBOX360). The CELL in the PS3 is not SMP because the PPU and SPU can not execute the same binaries and the cores are asimilar even though all cores have some method of accessing the main memory with a shared address space (although the SPUs also use a DMA read/write to main memory rather than direct access which would doubly qualify them as ASMP - but even without this memory difference, they would still be ASMP processing).
        • Re: (Score:2, Funny)

          by JackMeyhoff (1070484)
          Argh my eyes, dazzled by facts! Im blind!
      • by Eivind (15695)
        Quite simply, no.

        The S in SMP is symetry as in "several identical" parts anyway, not as in "a power of two".

        A star with 5 equal arms, equally spaced, is perfectly symetrical.
      • Re: (Score:3, Funny)

        by Eunuchswear (210685)
        No, they're using rotational symmetry, not reflection.

        Your data gets turned through 120 degrees as it moves from core to core, irritating, but better than having it come out sdrawkcab as sometimes happens with dual core processors.
    • by tji (74570)
      He's referring to the terminology.. "Symmetric" multiprocessing. Symmetric implies a balance, often a mirroring of equal sides.

      Obviously in the case of three cores, it's not going to be literally "symmetrical".

      He goes on to say "AMD offers that an odd number of processors can slice at that workload as well, just as efficiently", so it's not like he's spreading FUD or something...
  • by kiehlster (844523)
    So when does the race to unlock the fourth unused core on a triple-core processor start? What's Next? Hard drive platters?
    • by Lehk228 (705449)
      that is what i want to run, a fourth core that was disabled due to failing QC tests.
    • by level_headed_midwest (888889) on Monday September 17, 2007 @11:27PM (#20647533)
      There are a few possibilities:

      1. The core is there and locked off via microcode like the extra quads on a cut-down GPU (e.g. Radeon x1900GT vs. x1900XT) and can be enabled with a microcode flash.
      2. The core is there but the fuses that connect it electrically to the rest of the die are blown, so it is there but not able to be enabled.
      3. The core was never there as the die only has three cores in it in the first place- you have a fully-functional piece of silicon, so there is nothing extra to enable.

      Either way, it's really long odds you'll get a free core enabled. Nobody has been able to even upward-unlock the K8's multiplier and I know for a fact that is set in microcode (some guys on ExtremeSystems got a JTAG and found that out but not how to change it.) They will probably use the same method they used to disable one core on a dual-core die and sell single-core Manchester and Toledo-die chips and AFAIK nobody has unlocked any of those. I bet they have a few of the X3s be X4s with a bad die, but the X4 is a darn big chip at nearly 300 mm^2 and the cost reduction by using a native 3-core die would be mighty attractive to them so I guess that most will be #3 then.
  • by Bryan Ischo (893) * on Monday September 17, 2007 @10:36PM (#20647159) Homepage
    Wouldn't it make sense to sell any part that had at least one working core? Meaning that if in making quad-core chips, W% of them ended up only having one working core, X% had 2, Y% had 3, and Z% had four, wouldn't it make the most sense to sell all of these chips?

    This implies that they have a way to use all four cores independently. Maybe they can't; maybe one core is "special", like the "master" core that has to be working for anything to work. Also this implies that the cores can detect that their sibling(s) aren't working and switch to a mode in which the sibling is not used at all.

    Also, a question - when a core doesn't function properly, is it somehow disabled completely so that it doesn't use any power? Or maybe a core that isn't being fed any instructions doesn't use any power anyway?
    • by sjames (1099)

      Rather than detecting the failure, they probably have a strap on the chip. It could be a simple wire in the package, or it could be on the surface where they can zap it with a laser to disable a core that didn't make the grade. IIRC that's what Intel did with the cache to make a celeron.

      The strapping would give them more options in the case that one core bins slower than the other 3. Derate the chip or zap out the slow core.

      It's a great way to raise their effective yield and keep prices down.

    • by Chris Snook (872473) on Tuesday September 18, 2007 @01:16AM (#20648195)
      The Barcelona/Phenom architecture allows each core (plus the northbridge) to run on its own power plane, and for cores to be turned off completely. Of course, core 0 is the bootstrap processor, so that core has to always be enabled, or they have to have a way to change which one is core 0 before it leaves the factory. Otherwise the BIOS won't be able to bring the other cores online.

      The idea of post-factory error detection isn't so far-fetched. If a chip passes QA, the sorts of defects you'll see later in its life are likely to be thermally induced, and the likelihood that the defect will manifest prior to loading of the BIOS is very low. You're not using the MMU or the FPU at all, you're not using much of the cache, you can be running at your minimum power setting, and you're not doing it long enough to heat up much. If a core gets marked bad due to an excess of MCEs, similar to how many systems can mark DIMMs bad on excessive multi-bit ECC errors, the BIOS simply doesn't need to bring it online at boot time. Even if core 0 is the faulty one, you can probably load just enough of the BIOS to bring a good core online and finish booting, since you're not straining it enough to cause thermal problems, and you're only using a tiny fraction of the instruction set and die transistors. This sort of High Availability feature probably won't make it to the desktop right away, but as core counts keep increasing, it's inevitable.
      • I forgot to mention, s/390 mainframes already do this, and they do it online, without any data loss. The chips have two cores that do the same work in parallel. If they disagree on the result, they back up and try again. If they disagree again, they mark the chip bad and move it over to a hot spare. Of course, they're not exactly targeted at the desktop market.
      • by Bryan Ischo (893) *
        Great post. I can't believe that my lame post got modded 4 but your informative one is still at 2.
    • Wouldn't it make sense to sell any part that had at least one working core? Meaning that if in making quad-core chips, W% of them ended up only having one working core, X% had 2, Y% had 3, and Z% had four, wouldn't it make the most sense to sell all of these chips?

      Not at the cost of supporting all the different SKUs. Supporting all the parts with the different test programs, piece parts, and managing inventories can result in less profit than just scrapping the silicon.

  • Just a binned part? (Score:4, Informative)

    by Erich (151) on Monday September 17, 2007 @10:38PM (#20647191) Homepage Journal
    The picture clearly has a quad-core processor in it. Is this just a binned quad-core processor where one of the cores has a defect (like what Sony did with their Cell chip?) Or is it something separate, where they use the florplan for an L3 or something?

    And why should ``symmetric'' imply even? It merely implies that all cores see memory with the same class of service. And, in reality, aren't most AMD multiprocessors cc-NUMA machines, not SMP?

    For most workloads, if they are fairly multithreadable, 3 processors available will be just fine. I know of very few workloads that require an even number of processors, and even if it were the case that the task were split into an even number of threads, the OS should have no problem scheduling on a reduced number of processors.

    Hey, doesn't the XBox 360 have a 3-core PPC in it?

    • by suv4x4 (956391) on Monday September 17, 2007 @11:00PM (#20647363)
      The picture clearly has a quad-core processor in it. Is this just a binned quad-core processor where one of the cores has a defect (like what Sony did with their Cell chip?)

      This is what the article authors suggest, but no, it's a separate architecture. While I suspect it's possible a subset of the 4-core Phenoms to be relabelled as 3-core Phenoms, the bulk of 3-core Phenoms will be built as 3-core parts from the very start.

      And, to add insult to injury, this is a quad-core Phenom on the picture, since it's all the authors of the fine article could find. In other words, they are idiots.
      • by Erich (151)
        You don't make floorplans that aren't rectangular... what would they do with the extra space?
  • This is an interesting business strategy that plays to AMD's ability to sell partially-defective quad-core dies (confirmed by AMD in http://www.news.com/8301-13579_3-9780049-37.html [news.com]). It should let AMD increase revenues per wafer, offer a nice mid-performance product, and play some product mix games with clocking -- selling a processor as either a higher speed triple-core or a lower-speed quadcore chip. And there's no reason why core count must be powers of two or even or anything.

    Yet I can't help but won
    • by click2005 (921437)
      Surely Intel must have a bin full of quad core CPUs where one core failed QC. Whats to stop them selling those too?
      • Intel was smart and used MCM. 2 dual core chips pasted together. AMD is doing the tri-core thing out of desperation, even one of their own guys recently said they made a mistake trying to wait for "real" quad core. Now they're paying the price and this is a silly effort to make back some of their losses.
      • by level_headed_midwest (888889) on Monday September 17, 2007 @11:33PM (#20647567)
        Intel makes the Core 2 Quads by putting two Core 2 Duos together under the heat spreader. They are separate dies- go buy a Q6600 and pop the IHS off and look at the two separate dies yourself if you need proof. Intel tests the dies before they are mounted on the substrate, so a die with a bad core never makes it into the C2Q. Another fully-functional die is used in its place. The die with one bad core is either sold as a Celeron 4x0 or thrown away as defective. Intel doesn't make a single die with four cores like AMD is doing. Once they do, then they will have to worry about what to do with a quad-core die with one bad core. They can either pitch it, sell it as a 3-core, or disable another core and sell it as a dual.
    • by Rakishi (759894)

      Yet I can't help but wonder if customers will think twice about buying a 75% functional chip.
      Why would they care? They never did before. Low clock cpus were just those that filed to run properly at high clock rates. Mid end video cards were the ones were some part of a high end one failed.
    • by Bobartig (61456)
      There may be a perceived stigma to purchasing a 75% functional chip, but really this is no different from any other CPU yield situation. If you buy a 2.4 GHz proc instead of a 3.0 GHz of the same family, you're buying the same chip that doesn't run as well/efficiently.

      So in this case, you might be buying a chip where 1 core only ran at 1.8 GHz, and the rest run at 2.4 GHz, so it's a 3x 2.4 GHz because it didn't cut it as a quad core part.

      At any rate, it sure beats junking parts that are still very effective
      • At any rate, it sure beats junking parts that are still very effective processors.

        Not necessarily, the cost to support additional parts may be more than just scrapping the silicon.
        It costs just as much to manage a 4-core part as a 3-core but the 3-core would be sold at a lower price. Further, as yield on the 4-core improves you start running into issues supplying 3-cores run into cases where to support SKU demands you sell working 4-core parts as 3-cores and earning less for that good silicon.

    • by deniable (76198)
      People bought the 486SX. Heck, how many people know what's in their machine. No, slashdot is not an acceptable sample.
  • Even? What the hell? (Score:4, Informative)

    by sholden (12227) on Monday September 17, 2007 @10:43PM (#20647227) Homepage
    Symmetric just means the processors are equivalent (they all do the same generic tasks)... As opposed to an asymmetric system where different processors are assigned different roles (one does interrupts, one does graphics, one does IO, etc)...
  • Here is the definition from wikipedia [wikipedia.org].

    Symmetric multiprocessing, or SMP, is a multiprocessor computer architecture where two or more identical processors are connected to a single shared main memory. Most common multiprocessor systems today use an SMP architecture.

    SMP systems allow any processor to work on any task no matter where the data for that task are located in memory; with proper operating system support, SMP systems can easily move tasks between processors to balance the workload efficiently.


    SMP refers to the fact that all the processors are identical and share the same memory (in contrast to NUMA designs like multi-chip Opteron systems). However, I've seen more and more people refering to cache coherent NUMA designs like multi-core opteron and the upcoming CSI based intel systems as SMP systems which, while a stretch of the definition, is at least reasonable.

    Suggesting that SMP has anything to do with having an even number of processors is just DUMB. It may be the case that SMP systems usually have an even number of cores (I don't know) but that's not what the writeup or article seem to be saying.
  • SMP? (Score:3, Insightful)

    by Door-opening Fascist (534466) <skylar@cs.earlham.edu> on Monday September 17, 2007 @11:32PM (#20647563) Homepage
    I always thought SMP meant that all the processors are treated equally as far as available resources, and had nothing to do with the number of processing units available.
  • ..when more than 4GB's of ram will become the norm and software makers will be forced to make and support decent x86-64 ports. Give them 5-10 more years to make and support decent multi-threaded software.
  • by Joce640k (829181) on Tuesday September 18, 2007 @12:55AM (#20648073) Homepage
    Here's what's going on:

    AMD has a process which can put X number of transistors on a chip.

    One of their cores needs Y transistors.

    A qualified engineer with years of training in advanced mathematic divided X by Y and got the number "3".

    So... the chip got three cores.

    Mystery solved!
  • Does the extra space "left over" mean they can do an on-die GPU for cheap?

    Is that part of their roadmap?
  • So everyone's talking about how much pain AMD is in. Bleeding cash 24x7. So they've spent money on R&D for a 3 core processor!? Are you kidding me? Did they REALLY think there's gonna be a big market for three core computers!?

    This seems like almost as bad of a decision as Intel made going with Netburst. The difference being Intel could afford to make a big mistake. AMD doesn't have that luxury, and their new luxury might be going bankrupt. Sure, Intel went with Netburst because it solved several
  • Reminds me of the 486SX. Basically a 486DX chip with a defective FPU, disabled, then sold. At least the early batches were, anyway. This is an excellent move by AMD. Somewhere in between dual and quad-cores at competetive prices, which I suspect would be somewhere closer to dual-cores.

...there can be no public or private virtue unless the foundation of action is the practice of truth. - George Jacob Holyoake

Working...