PCIe 8.0 Announced With 256 GT/s For AI Workloads (nerds.xyz) 37
BrianFagioli shares a report from NERDS.xyz: PCI-SIG says PCI Express 8.0 will hit a raw bit rate of 256.0 GT/s, doubling what PCIe 7.0 offers. The spec is expected to be ready by 2028, and the goal is to support massive data loads from AI, machine learning, edge computing, and even quantum systems. The group says PCIe 8.0 will allow up to 1 terabyte per second of bidirectional throughput with a full x16 configuration. They're also looking at new connector designs, improving protocol efficiency, reducing power use, and maintaining backward compatibility.
Timeline (Score:5, Informative)
Re: Timeline (Score:2)
Re:Timeline (Score:4, Interesting)
Other than servers and high end workstations, there's also absolutely no need for even pcie5 yet. The most powerful gpus barely need pcie4 still, and ssds are about 100M/s for 4k transfer speeds, the most important metric for 99% of users other than marketing wank.
Add to this the fact that faster speeds make hotter components. And more importantly the fact that routing even pcie5 traces is already veering on the edge of black magic... The money quote from tomshardware on pcie8 https://www.tomshardware.com/t... [tomshardware.com] :
Engineers will enter uncharted territory, as no current copper interconnect standard can boast such a data transfer rate, especially over distances of tens of centimeters.
Sounds a lot like they have no idea yet on how to accomplish the speeds required, but since they have a target of a new spec every 3 years they are hoping to figure it out down the road.
Doubling the data rate has one very interesting use case though. You can halve the lanes dedicated to any device by half without impacting throughput. Imagine e.g. a beowulf cluster^W^W 100 disks connected to a threadripper, each on a dedicated non-saturated link... Or any other devices, really. My personal pet peeve of having to buy a second cpu into a machine, and having to deal with numa, just to get all the required hardware into the machine might finally go away...
Re:Timeline (Score:5, Informative)
. The most powerful gpus
Let me stop you there. GPU's haven't defined the limits for PCI bandwidth for a while now. Parallel storage arrays for NVMe drives, and chip to chip interconnectors are the big use case for the bandwidth. Your PC is currently very much constrained in bandwidth as the motherboard has limited amount of lanes for certain tasks which get split into multiple duties. Take for example your GPU. Got a 16x GPU on the motherboard? It won't get 16x lanes if you share the slot next to it with a NVME riser since the 16x slots are almost universally multiplexed unless you a buying a high end threadripper board. Got 3 NVME drives? Congrats, the performance of one of them will absolutely crater when a high bandwidth USB device is plugged into the "wrong" port as even high end X870 boards can only connect 2 NVME slots to the processor itself while the rest go through a chipset and share their lanes with a myriad of other devices. And that's before you consider that there are actually PCIe 6.0 SSDs on the market https://www.micron.com/product... [micron.com]
But beyond that these products aren't designed for you. They are designed for the types of people who would put say multiple NVIDIA ConnectX Infiniband adapters together into a switch, or connect their PCIe 6.0 interface to 4 hosts concurrently providing each with 16x lanes.
The high performance computing industry laughs at your little toy GPU use case.
The money quote from tomshardware on pcie8
You misunderstood the money quote. The quote is about a massively parallel board edge interconnector, not the traces on the PCB. We absolutely are capable of doing fast signaling on the PCB itself and in single signals through to antennas and through some connectors, the issue here is connecting two PCBs together in a cheap way (currently one side of the interconnector is just a raw PCB without an actual connector at all, and this keeps costs low).
Re:Timeline (Score:4, Interesting)
Yeah all that is nice and dandy, and I agree with it, but this is exactly why I started my post with "other than servers and high end workstations". Because op was talking about motherboards, which is not exactly where you start talking about inifiniband. Notice also e.g. for your first paragraph that I explicitly mentioned dedicated lanes in my post, too.
Wrt the quote, I suppose I could have worded that paragraph better, but I thought that a quote talking about interconnects would be taken as talking about interconnects.
But let's not ignore traces either. Pcie5/6 are 16GHz Nyquist frequency already, with 6 having 4 signal levels at that. 7 is 32GHz for what I can gather, because it uses the same encoding as 6, and 7 looks to be 64GHz for the same reason. Let us remind ourselves now that already at pcie5 speeds the unevenness in the dielectric properties of the pcb caused by the weave of the fibers inside were enough to cause loss of signal... Now imagine what four times the speed and double the signal levels will do to that. You might as well go wireless by then, because the signal is going to want to be anywhere but stay in the trace. So it looks to be more of an optics game - I, for one, await in amazement for what they are going to have to do to make it happen.
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I could only speculate, I'm not present at the pci-sig table. Maybe this much - since pci-sig is composed of major hardware players, their designs shouldn't be too far removed from their own ability to manufacture stuff.
But doubling the speed is not an unreasonable target per se, whether you currently know how to manufacture it or not. Any less of an improvement would be kinda meh, and any more might be too much to bite off. In that sense you can probably announce the speeds of all new versions yourself. (W
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Because op was talking about motherboards, which is not exactly where you start talking about inifiniband.
I didn't start talking about infiniband, I finished talking about infinibad. I started talking about NVME cards, and I am already in that very real position myself where there are NVME drives on the market that I can't use to their full potential (not including the PCI-e 6 drives which I didn't even bother to looking up the price of) due to PCI-e constraints on the chipset and lane sharing. I have two identical drives in my system which present very difference performance when transferring to external SSDs
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I wish they did more with PCIe lanes. Mainly so we can get eGPUs as a mainstream option back, or other dedicated appliances that can be used on a bus instead of just the CPU and cards. For example, multiple TB5 lanes just for storage I/O or network I/O.
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Virtually all of your PC's hardware is connected to the CPU via PCIe. The exception is analog audio and a handful of the USB ports that are connected directly to the CPU, and the iGPU's video. Everything else is connected to the CPU via PCIe, either directly, or via the chipset, which is connected via PCIe.
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Other than servers and high end workstations, there's also absolutely no need for even pcie5 yet. The most powerful gpus barely need pcie4 still, and ssds are about 100M/s for 4k transfer speeds, the most important metric for 99% of users other than marketing wank.
It would be useful if the technology ever isn't absurdly cost prohibitive. Some uses off the top of my head:
- GPU cards without discrete VRAM powered entirely by unified memory
- CXL cards to add more memory
- AI accelerator cards
Re: Timeline (Score:2)
Internal development with the draft specification is already on everyone's roadmap. Product release of many vendors will be the same year as the final spec.
Only available with Windows 12! (Score:2, Insightful)
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Only available with new hardware equipped with Intel management engine, AMD Platform Security Processor, and assorted other baked in malware also. Pass
Perfectly Reasonable Power Draw (Score:3)
I mean, who doesn't have a smal RTG reactor in the back yard and an on-board fire extenguisher!
NVidia looks forward to melting even more mobos and PSUs in the future.
Re: Perfectly Reasonable Power Draw (Score:3)
RTGs have a very low power output.
bollocks (Score:4, Insightful)
the goal is to support massive data loads from AI, machine learning, edge computing, and even quantum systems
Nonsense. The goal is to have a faster bus. This is great no matter what you're doing with it because you can use fewer lanes to do the same job. All that shit is just buzzwording for attention. Look who it worked on.
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All the high-impact actors are pivoting their actionables using recent AI to leverage their productive flow. You're just not inspiring enough to know.
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256 GT/s For AI Workloads (Score:3)
Cool to have 256 GT/s for AI workloads, but how fast is it for other workloads?
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Some marketing person must have involved themselves in the process, and inserting AI is their latest fad.
Where’s the new Bottleneck now? (Score:3)
With PCI reaching these speeds, I’m left wondering; what is the bottleneck now? Is “storage” on these systems a silly concept because it’s essentially ALL high-speed cache in memory, or forced to be because slowing down for it makes PCI advancements pointless? Just wondering where or what the future challenge will be in our endless pursuit of moar and faaaaster.
Also, that whole backward compatibility thing? Stop it. Just fucking stop it already. It smacks of the stupidity when talking EV “horsepower”. Time to grow up and move on. No one makes plans on a calendar a fortnight from now. Not sure why we’re worrying about supporting shit even half a decade old when it’s gonna take another decade just to get this to any market beyond the highly specialized ones justifying it. F1 race teams do not worry about being compatible with anything other than F1. You either justify your specialization, or you don’t.
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On the backwards compatibility front, EV horsepower makes as much sense as a gasoline engine, sure we could say 'kilowatts' for both, but marketing loves the 'horse', especially since changing to kw would make the numbers go lower.
Problem on the compatibility front is that while you may safely ignore a 2005 PCIe adapter (or require such users to buy an adapter), breaking that compatibility form-factor wise also means breaking compatibility with 2025 adapters, which would be a much bigger problem. The most
Its the overhead of the "application stack" (Score:3, Funny)
what is the bottleneck now?
The overhead of applications created by stacking thirty something libraries on top of each other to solve a problem a CS sophomore could directly code up.
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With PCI reaching these speeds, Iâ(TM)m left wondering; what is the bottleneck now? Is âoestorageâ on these systems a silly concept because itâ(TM)s essentially ALL high-speed cache in memory
PCI isn't reaching these speeds any time soon. But that aside, the limiting factor depends on the workload. Which kind do you want to know about?
Also, that whole backward compatibility thing? Stop it.
Are you seriously saying you want less compatibility? Weirdo.
GT/s ? (Score:2)
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What is a GT/s? PCI-SIG technical workgroups will be developing the PCIe 8.0 specification with the following feature objectives (so, a press release)
Still stands for Gran Turismo I’d imagine, since our minds are practically racing around the ol’ clickbait track.
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It's basically marketing wank that was originally designed to sell DDR ram as, ex, "2400MT" when running on a 1200mhz bus.
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GT/s is not marketing fluff at all, really, and not started by just DDR folks. The term is used to unambiguously describe the base line rate of a channel. It has concrete definitions for the folks actual designing the PHYs on the bus. GT/s as base unit has been in every PCIE spec from at least 1.0 (and probably before). It's used to describe line rates for many channels, not just those used in PCIE. (i.e. DDR, various SERDES, etc. )
A single channel (or lane, or X1) PCIE Gen 8 device will have 256 GT/s *
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Close. Since Gen6, use of PAM4 encoding transfers 2 bits/transfer.
Before that, regular NRZ encoding transferred 1bit/transfer.
Gen6 is still 32GT/s, but approximately 64Gb/s.
Gen7 is 64GT/s, but approximately 128Gb/s
Giga-Teslas per second ?? (Score:3)
Honstly... https://en.wikipedia.org/wiki/... [wikipedia.org]
Why are we now using GT/s to mean "giga-transfers per second"? FFS
It's bad enough the people in the US use "milli-Teslas" to mean "metric tonnes".
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Whoah, slow down cowboy!! (Score:2)
Image the cool case LED animations ... (Score:3)
My gaming PC motherboard is on version 4, and I didn't buy that all that long ago.
Sure, but with PCIe 8 imagine the cool LED animations you could have in and on your PC case without taking a noticeable hit during gameplay. I mean we could probably replace all of those LEDs with tons of tiny OLED displays. :-)