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Intel Hardware

Pentium 5 - a Rare Look Into the CPU That Could Have Been But Never Was (wccftech.com) 31

Long-time Slashdot reader alaskana writes: In late 2022 it was revealed that early samples of what was to be the "Pentium 5" processor, codenamed Tejas and Jayhawk were in development and made it as far as being released to board partners for evaluation. A few of these samples made it (of course) onto Ebay and then — not surprisingly — into the hands of a YouTuber. To be fair, tech site Anandtech arguably got the first scoop on this P4 successor way back in 2004, but that story seemingly never gained much traction at that time.

They wrote that Intel Prescott CPUs "could hit 5GHz+ but had huge power and temperature numbers, but Tejas was expected to clock higher than Prescott — with Intel chasing the huge 10GHz CPU clocks within 10 years between 2000 and 2011 — but it ended up not happening at all."

In what was supposed to be a continuation of the "GHz is king" days of the early aughts, the Pentium 5 was in spirit a continuation of the "faster-is-better" philosophy of the P4 architecture, efficiency be damned. Speeds in excess of 7 GHz(!), and a pipeline upwards of 50 stages were rumored to be targeted by Intel, but reality (and physics) reared their ugly heads as always. WCCF Tech transcribed the remarks of Intel engineer Steve Fischer, who was involved with the project. "The thing had a pipeline depth of around 50 stages and an expected clock target at one point north of 7 GHz. I call the thing "the Death Star of processors" and half-jokingly reasoned that consumer acceptance of liquid-cooled chassis would not be a big deal."

Intel kicked off Project Tejas in 2003, expected in 2004 and later pushed into 2005 after issues forced Intel to redesign the chip. Before the company could do that, the Tejas Project was shelved on May 7, 2004. In the end efficiency and parallelization was to be the rule of future CPU development, but the fact that Intel had (at least briefly) had planned on taking the P4 paradigm just a wee bit further with a true Pentium 5 is a fascinating look into the past of a future that never was to be for the venerable Pentium line.

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Pentium 5 - a Rare Look Into the CPU That Could Have Been But Never Was

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  • by dfghjk ( 711126 ) on Saturday October 07, 2023 @04:56PM (#63908915)

    "...efficiency be damned. ...but reality (and physics) reared their ugly heads as always."

    As always? Efficiency be damned? Since when? This is very definition of hindsight analysis. Power and clock speed limitations were DISCOVERED at this time, the very opposite of "as always". Power efficiency in this days was NOT a consideration for desktop processors.

    "...but the fact that Intel had (at least briefly) had planned on taking the P4 paradigm just a wee bit further..."

    OF COURSE THEY DID! They did not yet understand that the design approach was doomed. RAMBUS was integral to the design and Intel had a MASSIVE investment in both hyper-pipelining and RAMBUS. Of course Intel planned on follow-ons to the P4!

    It's a shame that morons are all that is left of this site.

    • by 93 Escort Wagon ( 326346 ) on Saturday October 07, 2023 @05:30PM (#63908965)

      It's a shame that morons are all that is left of this site.

      Given this observation, I am obliged to point out that *you* are still on this site... ;-)

    • As always? Efficiency be damned? Since when? This is very definition of hindsight analysis. Power and clock speed limitations were DISCOVERED at this time, the very opposite of "as always".

      I would argue that the P4 was the first real indication that ramping up power for clock speed was becoming a dead end, but really it was a long road, so saying "as always" is sort of fair. They had long since needed to add heat sinks, then fans, and then more power to the CPU with an extra connector.
      Overall, given how ridiculous the 4GHz P4 was, that the followup chip had to be canceled seems about right.

    • by Sique ( 173459 ) on Sunday October 08, 2023 @06:49AM (#63909627) Homepage
      The Israel Development Center, IDC, which designed the Pentium M chips, knew that already at the time the Pentium 4 came out. Thus they based their designs on the old Katmai and Coppermine cores of Pentium III fame, increased their L2 caches while at the same time introduced SpeedStep to power off parts of the (quite energy intensive) L2 caches if not needed.

      There has never been a dedicated Pentium 4 mobile chip because of its power consumption, and as power consumption of the P4 (especially compared to the AMD lineup) proved to be a damning issue, Intel cancelled Pentium 4 development and based their next processors on the Pentium M, giving them the Intel Core Solo and Core Duo name.

  • by kriston ( 7886 ) on Saturday October 07, 2023 @05:12PM (#63908925) Homepage Journal

    With a 50-stage pipeline, how many hyperthreads were there?

  • by 93 Escort Wagon ( 326346 ) on Saturday October 07, 2023 @05:22PM (#63908943)

    I'm still waiting for my PowerBook G5, dammit!

    • > I'm still waiting for my PowerBook G5, dammit!

      IBM had told Jobs "no chance" well before the rumors were allowed to circulate.

      That forced Apple's transition to Intel.

      Sadly Jobs had become complacent with G5 desktop and the Intel/PPC emulation didn't get the attention it needed during the G4 era.

  • by Pezbian ( 1641885 ) on Saturday October 07, 2023 @05:24PM (#63908945)

    PIII Tualatin chips were the basis for the Pentium M which led to the Core CPUs.

    Pentium M was a gangster. I had a ThinkPad R40 with a 1.4GHz P-M I undervolted and optimized for power consumption where I could get the machine pulling 5W while writing. At full piss, it could outpace a Pentium 4 3.0GHz.

    • by bill_mcgonigle ( 4333 ) * on Saturday October 07, 2023 @05:50PM (#63908993) Homepage Journal

      The M came out of Intel's rogue Israel research facility which had escaped Marketing's rule of terror.

      Ironically it looks like Marketing is back in charge again.

      • by kriston ( 7886 )

        Rogue? I thought it was their tick/tock competitive development process.

        • The Pentium M predates the tick/tock paradigm, though it is a bit hyperbolic to describe IDC as a "rogue" facility when it was doing the thing it was assigned to do.

          They were tasked with making low-power PIII derived cores for mobile while the new PIV cores would be used for performance products. Eventually they got to the point where the Pentium M could match the performance of a PIV and was still at a lower TDP, at which point there was no longer much of a reason to make PIVs.

          It wasn't until after the mob

  • The brain computes exaflops with less than 25 watts .. so how are they framing Pentium 5 as a physics issue? It's a materials, architecture, and chemistry issue.

    • by Anonymous Coward
      The brain is probably a little too analog for floating point operations to make sense.
    • The brain also produces an astonishingly high amount of errors and is, at times, incapable of performing even the most rudimentary mathematical operations.
    • Could you please clarify what you mean by the "brain computes exaflops". I am guessing you mean that there are exa-gates so to speak in the number of synapses. If that is what you meant then you may be correct that ex-"flips" occur per second, exa- gate transitions or synapse depolarizations. But a flop is a floating point operation, and for us to compute just one, or even to do a a simple integer calculation, might take a fraction of a second or quite a few seconds depending on how many decimal places a

  • by marples ( 10436424 ) on Saturday October 07, 2023 @08:55PM (#63909171)
    I worked for Steve Fischer. Tejas was originally targeting 7.4 GHz and all the architects were asked to sign a "signed in blood" poster claiming they would commit to reaching the target ... it was Siva Yeramilli's first CPU project after his Vermillion (TV platform) failure ... it never taped out. At that time we had been recently creamed by AMD hitting 1GHz first and also beating us to the 64-bit extensions (also creaming our Yamhill top-secret 64-bit panic response), so Folsom architecture was smarting. The Austin team was all of the principal engineers hired from Motorolla (for ungodly salaries) as part of Albert Yu's greenfield strategy but we quickly learned they weren't the best architects / don't get me wrong some were phenoms but most were just average and given way too big a challenge (in addition to redesigning mobile -and- migrating intel from ihdl to verilog). madness. Yu was asking us to give 110% every year and blaming us when we failed to deliver, while still jacking up expectations. this was intel's inflection point into mediocrity that could only be maintained by massive investment in fabrication vs architecture stagnation.
    • by Anonymous Coward

      This cycle repeats over and over at Intel. They make huge mistakes, reorganize (fire/hire the managers) then claw back to the top, then corporate dumbasses take over and the cycle repeats.

      They always have brilliant developers/engineers and absolute morons at the top.

      Their biggest successes always come out of groups working alone in secret that top management barely knows they exist.

    • And here I thought all of the Phenom architects were at AMD. Or perhaps they just moved over there after a brief stint with Intel.
  • by MtViewGuy ( 197597 ) on Saturday October 07, 2023 @10:38PM (#63909275)

    The Tejas CPU idea was a dead end because it would have required massively big power supplies just to keep it going. And the heat generated would have caused too many problems, too.

    Fortunately, Intel wised up and used the Pentium III-M design for what because the Conroe multicore CPU's. We get all the benefits of Tejas but with vastly lower power consumption and system cooling requitements.

  • I remember my freshman year at MIT someone talking about how a breakthrough was going to lead to CPUs that top out at 5Ghz. This was when we all had PC's between 16 and 50 MHz.

    This is just one of many times I saw a grapevine prediction, plus a casual discussion with some basic math, borne out over decades. It always made me feel like the published stuff was just noise.

Every nonzero finite dimensional inner product space has an orthonormal basis. It makes sense, when you don't think about it.

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