Google Used Reinforcement Learning To Design Next-Gen AI Accelerator Chips (venturebeat.com) 18
Chip floorplanning is the engineering task of designing the physical layout of a computer chip. In a paper published in the journal Nature, Google researchers applied a deep reinforcement learning approach to chip floorplanning, creating a new technique that "automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area." VentureBeat reports: The Google team's solution is a reinforcement learning method capable of generalizing across chips, meaning that it can learn from experience to become both better and faster at placing new chips. Training AI-driven design systems that generalize across chips is challenging because it requires learning to optimize the placement of all possible chip netlists (graphs of circuit components like memory components and standard cells including logic gates) onto all possible canvases. [...] The researchers' system aims to place a "netlist" graph of logic gates, memory, and more onto a chip canvas, such that the design optimizes power, performance, and area (PPA) while adhering to constraints on placement density and routing congestion. The graphs range in size from millions to billions of nodes grouped in thousands of clusters, and typically, evaluating the target metrics takes from hours to over a day.
Starting with an empty chip, the Google team's system places components sequentially until it completes the netlist. To guide the system in selecting which components to place first, components are sorted by descending size; placing larger components first reduces the chance there's no feasible placement for it later. Training the system required creating a dataset of 10,000 chip placements, where the input is the state associated with the given placement and the label is the reward for the placement (i.e., wirelength and congestion). The researchers built it by first picking five different chip netlists, to which an AI algorithm was applied to create 2,000 diverse placements for each netlist. The system took 48 hours to "pre-train" on an Nvidia Volta graphics card and 10 CPUs, each with 2GB of RAM. Fine-tuning initially took up to 6 hours, but applying the pre-trained system to a new netlist without fine-tuning generated placement in less than a second on a single GPU in later benchmarks. In one test, the Google researchers compared their system's recommendations with a manual baseline: the production design of a previous-generation TPU chip created by Google's TPU physical design team. Both the system and the human experts consistently generated viable placements that met timing and congestion requirements, but the AI system also outperformed or matched manual placements in area, power, and wirelength while taking far less time to meet design criteria.
Starting with an empty chip, the Google team's system places components sequentially until it completes the netlist. To guide the system in selecting which components to place first, components are sorted by descending size; placing larger components first reduces the chance there's no feasible placement for it later. Training the system required creating a dataset of 10,000 chip placements, where the input is the state associated with the given placement and the label is the reward for the placement (i.e., wirelength and congestion). The researchers built it by first picking five different chip netlists, to which an AI algorithm was applied to create 2,000 diverse placements for each netlist. The system took 48 hours to "pre-train" on an Nvidia Volta graphics card and 10 CPUs, each with 2GB of RAM. Fine-tuning initially took up to 6 hours, but applying the pre-trained system to a new netlist without fine-tuning generated placement in less than a second on a single GPU in later benchmarks. In one test, the Google researchers compared their system's recommendations with a manual baseline: the production design of a previous-generation TPU chip created by Google's TPU physical design team. Both the system and the human experts consistently generated viable placements that met timing and congestion requirements, but the AI system also outperformed or matched manual placements in area, power, and wirelength while taking far less time to meet design criteria.
Do you want Zero One? (Score:2)
Because this is how you get Zero One.
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Because this is how you get Zero One.
The Singularity is unavoidable.
The only question is who will own it.
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The Singularity is unavoidable.
The only question is who will own it.
Is that even a question? Sure Google makes pleasing mouth noises and open sources TensorFlow, but how many people who don't work for Google can even make it run, nevermind do something useful? To say nothing of the various closed source libraries. That number is not zero, and may even include some Slashdotters, but it is a very short list in a world of 7 billion. If TensorFlow wasn't open source, how many people could recreate it? I'm guessing approximately as many people as can create full featured op
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Sure Google makes pleasing mouth noises and open sources TensorFlow, but how many people who don't work for Google can even make it run
I haven't had any problem getting it to run. My son used Tensorflow/Keras for a high school project.
You can rent TPUs online by the minute.
If TensorFlow wasn't open source, how many people could recreate it?
Why would they need to?
If I write C++ code, I don't need to write my own compiler.
Likewise, if I build a NN model, I don't need to write my own gradient descent library.
The interesting work is the model, not the low-level libraries.
Re: Do you want Zero One? (Score:2)
The interesting work is the model, not the low-level libraries.
For someone with *your* personality, maybe. Other kinds of people may enjoy pushing the boundaries of languages, implementations, and programming techniques, much like there are still theoretical physicists in the world of engineers.
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You're assuming they've implemented the right abstraction of "neural net". This isn't at all clear. They've implemented ONE abstraction, and it pretty much works, but there are lots of places where they made decisions that are questionable.
OTOH, it can probably do anything any other neural net could do. But remember, so could a Turing machine.
The theory of neural nets is very incomplete, and doesn't allow specification of things like "ideal feedback configurations". Those are, at most, "rule of thumb" k
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If the singularity occurs, the question isn't who will own it, the question is who it will 0wn first
This is big news. (Score:2)
OK For RTL I Suppose (Score:2)
From the description, this seems to be placement of synthesized logic that comes with timing constraints. This is good, placement and layout of synthetic RTL is tiresome and semi manual drudge work.
However there are plenty of analogish circuits that this would entirely mess up - i.e. digital gates, but very analog in nature - buffers, PLLs, entropy sources, PUF cells, intrusion detection circuits etc. These are all layout critical things which no AI today is going to get right. These are all present in pret
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Yes. We humans will continue to eke out a living in the shrinking margin of work that can't be automated. Yet.
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Not the one I was thinking about, and probably not the best example of this
https://www.damninteresting.co... [damninteresting.com]
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That one was indeed interesting, but probably not useful. It came up with a fragile design.
It is a fine example of a digital circuit which is exploiting the analog properties of the gates. This is basically what my group does, but in a much more controlled way.
I think one mistake was to make it asynchronous. The circuit is inevitably either making it's own clock(s) or extracting clocks from the input data.
Give it a clock and let the algorithm make synchronous logic. The genetic algorithm cogitates on the ne
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The paper showed that it would fail with small variations in temperature. That's hardly 'works between 0C and 70C' datasheet behaviour.
That isn't to say you can't make it resilient in that fashion, but the example did not.
With ML it is simpler - just train it over bigger data sets covering the process, voltage and temperature variation. The compute requirements go up cubically which is not great unless you sell CPUs.
RL was preceded by genetic algorithms ... (Score:2)
... as a quick google of 'genetic algorithms for chip floor plans' will show. Whether its a 'reward' or a 'fitness' function it's the same diff.
BUT this announcement follows on the heels of Deep Mind's announcement that 'all you need is reinforcement learning' so one could assume that Google is pushing reinforcement learning as 'the next big thing' even though it's been around for a couple of decades. Likely they have patents they want to exercise in some way?