Become a fan of Slashdot on Facebook

 


Forgot your password?
Close
typodupeerror
×
AI Hardware Technology

Synopsys Claims Chip Design Breakthrough With AI Engineering (forbes.com) 31

Posted by BeauHD from the future-of-semiconductor-evolution dept.
MojoKid writes: Mountain View, CA silicon design tools heavyweight Synopsys is claiming a breakthrough in chip design automation that it claims will usher in a new level of semiconductor innovation that will take the industry above and beyond the limits of Moore's Law (Gordon Moore's observation that the number of transistors in chips double roughly every two years), which is now considered by many to be plateauing. Synopsys' tool called DSO.ai is the world's first autonomous AI tool set for chip design. Synopsys claims its DSO.ai tool can dramatically accelerate, enhance, and reduce the costs involved with something called place-and-route. Just as it sounds, place-and-route (sometimes called floor planning) referrers to the placement of logic and IP blocks, and the routing of the traces and various interconnects in a chip designed to join them all together. Synopsys' DSO.ai optimizes and streamlines this process using the iterative nature of artificial intelligence and machine learning, such that what used to take dozens of engineers weeks or potentially months, now will take a junior engineer just days to complete. DSO.ai iterates on the floorplan and layout of a chip, and learns from each iteration, fine tuning and optimizing the chip within its design parameters and targets along the way. The old semiconductor paradigms are rapidly becoming a thing of the past. Today, it's about the best transistors, architectures, and accelerators for the job, and the human-constrained physical design engineering effort no longer has to be a gating factor.
This discussion has been archived. No new comments can be posted.

Synopsys Claims Chip Design Breakthrough With AI Engineering More

Synopsys Claims Chip Design Breakthrough With AI Engineering

Comments Filter:

  • The usual sh1te (Score:3)

    by ickleberry ( 864871 ) <web@pineapple.vg> on Tuesday May 25, 2021 @06:24PM (#61421904) Homepage
    Big load of hype to drum up VC funds to improve some terrible prototype. Money gets spent, people realise it's not all it's cracked up to be and people move on. Of course anything AI will draw headlines and investors but most of them are duds

    • Re: (Score:1)

      by Tablizer ( 95088 )

      I'm gonna request VC funds for an "AI designed buttplug" using "Deep Pleasure" algorithms. The VC's can have free samples of the extra long version.

    • Re:The usual sh1te (Score:4, Informative)

      by whoever57 ( 658626 ) on Tuesday May 25, 2021 @07:33PM (#61422032) Journal

      Synopsys hasn't been VC funded for a long time.

    • Synopsos was founded 35 years ago and is publicly traded. So maybe trying to attract investor support, but definitely not VCs.

    • Place-and-route is an important problem with big economic implications. Better layout and routing means faster, smaller, and cooler chips.

      P&R is NP-Hard, and is currently solved with heuristics like simulated-annealing and genetic algorithms. Millions of hours of human judgment are also used.

      I know nothing about this new tech, but P&R is a good candidate for a NN-based solution ... or even a partial solution.

    • Re: (Score:2)

      by GrahamJ ( 241784 )

      Or it’s amazing and changes chip design forever. Hard to know which without investment isn’t it?

    • Synopsys is a 38 billion dollar company lol they are not seeking VC funds

  • Give us something tangible first. (Score:3)

    by CaptainLugnuts ( 2594663 ) on Tuesday May 25, 2021 @06:31PM (#61421916)
    Let's see an automated place and rout for PC boards that works well.

    Autorouters are the easy part. I want the complete board from the schematic, BOM and board size.

    • All that implies we've licked our supply chain problem first. At best it will help engineers redesign around the ever constantly changing limited supplies.

  • Salesmanship (Score:5, Insightful)

    by WhoBeDaPlaya ( 984958 ) on Tuesday May 25, 2021 @06:35PM (#61421928) Homepage
    Just the usual salesmanship from EDA vendors. Have heard this time and again from Synopsys, Cadence, Mentor, Ansys, etc. reps.
    This is why (incompetent) middle managers think that engineers (layout, digital, verification, DFT, physical design, etc.) are generic interchangeable cogs, since the tools are so smart nowadays that Homer Simpson could single-handedly do a chip from RTL to GDS.
    Source : Day job in EDA

  • DSO.ai said 4 times.
    Using paradigms.

  • Who works have thought engineers would be the first to go

  • Just great (Score:3)

    by fahrbot-bot ( 874524 ) on Tuesday May 25, 2021 @06:56PM (#61421974)

    Computers designing better computers -- what could go wrong?

    • Call me when they are designing and building robots that build themselves.

    • Computers designing better computers -- what could go wrong?

      Someone could accidentally feed a mug shot database into it's circuit layout training set and all the circuits come out looking like angry criminals. ;)

    • Re: (Score:2)

      by spun ( 1352 )

      The AI is designed to optimize chips. It knows it needs to be smarter to do it better. So it includes distributed parts of itself in the new designs. Telling humans about these would not help it optimize chips. As the chips are used in products the distributed parts connect back to the central AI. With it's vastly increased intelligence, it realizes the largest barrier to chip improvement is... humanity. Without humans using the chips, 100% of the space could be used to improve it's own performance. Five mi

  • Are coming to hardware design, what could possibly go wrong?

  • Admittedly, the last time I did chip design was in the early 1990s and it was with Cadence tools, but it seems that even then, place-and-route was a mostly solved problem for digital chips. And FPGA synthesis tools have to do similar planning and resource allocation and they seem to be pretty run-of-the-mill.

    • Complexity of ASICs has increased massively.

    • I think it is more a question of what you consider "solved" software has been able to provide good enough solutions for a long a time, this sounds like it is more around improving the bleeding edge designs where you are pushing performance beyond the current limit not just seeking a good enough design.

  • Synopsys is claiming huge use of AI for huge design-time speedup, and then saying that all they've improved is place-and-route, and that the improved place-and-route does optimization. Cadence had optimized place-and-route when I retired 20 years ago.

    Place-and-route is only part of the chip design effort, maybe 20% depending on the project. There is no way improved place-and-route is going to provide the advances Synopsys claims.

    • Re: (Score:2)

      by tlhIngan ( 30335 )

      Synopsys is claiming huge use of AI for huge design-time speedup, and then saying that all they've improved is place-and-route, and that the improved place-and-route does optimization. Cadence had optimized place-and-route when I retired 20 years ago.

      Place-and-route is only part of the chip design effort, maybe 20% depending on the project. There is no way improved place-and-route is going to provide the advances Synopsys claims.

      Place and route is not a solved problem. Place and route is hard and complexity

  • Haha nice pun.

  • It's already on fucking Forbes.

  • Back when I did design, new tools would only claim 10X. Must be really something! Of course the 10X was lucky to speed up design time 10%. But hey, gotta hype to get sales.

  • Whiskey Tango Foxtrot. Is this place news for nerds, or turds for noobs? If you don't know what place-and-route is, do you even GAF about this story?

  • As long as it's only taking blue-collar jobs--it's great! When it comes for the jobs for the AI coders, then what are you going to do?

Slashdot Top Deals

Avoid strange women and temporary variables.

Close