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TSMC Update: 2nm in Development, 3nm and 4nm on Track for 2022 (anandtech.com) 78

Posted by msmash from the shape-of-things-to-come dept.
For TSMC, being the world's largest foundry with nearly 500 customers has its peculiarities. On the one hand, the company can serve almost any client with almost any requirements. On the other hand, it has to stay ahead of everyone else both in terms of capacity and in terms of technology. As far as capacity is concerned, TSMC is unchallenged and is not going to be for years to come. From a report: As for fabrication technologies, TSMC has recently reiterated that it's confident that its N2, N3, and N4 processes will be available on time and will be more advanced than competing nodes. Early this year TSMC significantly boosted its 2021 CapEx budget to a $25-$28 billion range, further increasing it to around $30 billion as a part of its three-year plan to spend $100 billion on manufacturing capacities and R&D. [...] TSMC's N5 family of technologies also includes evolutionary N4 process that will enter risk production later this year and will be used for mass production in 2022. [...] In 2022, the world's largest contract maker of chips will roll out its brand-new N3 manufacturing process, which will keep using FinFET transistors, but is expected to offer the whole package of PPA improvements.
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TSMC Update: 2nm in Development, 3nm and 4nm on Track for 2022 More

TSMC Update: 2nm in Development, 3nm and 4nm on Track for 2022

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  • 2nm! 2! and the 6502 was 8um (Score:3, Informative)

    by Anonymous Coward on Monday April 26, 2021 @04:10PM (#61316786)

    8um is 8000nm

    That's just nuts!

    • Re: (Score:1)

      by Anonymous Coward

      .. that would translate that the APC would be approx 10mm. (610mm x 320mm w/ 4100 3-input NOR gates (note: not counting core-rope ROM and core-based RAM)

      I could draw the masks with a sharpie - at scale.

      2nm means a mouse farts within 50' (15m) it's going to knock the mask out of alignment.

      Good luck to those boys and girls in pulling this off.

      • Re:2nm! 2! and the 6502 was 8um (Score:5, Informative)

        by solidraven ( 1633185 ) on Monday April 26, 2021 @05:36PM (#61317066)
        Read the actual literature, stop believing the numbers! If it were actually 2 nm that might be true, but it really isn't 2 nm, not even close. The core of the issue is that TSMC has been decreasing that number without actually decreasing transistor size respectively. To give you some funny numbers: TSMC's 10 nm process had about half the transistor density of Intel's 10 nm process, Intel's 14 nm process is about 50% more dense than TSMC's 14 nm process. Heck, TSMC's 7 nm is still less dense than Intel's 10 nm process. Generally Intel is the leader of the pack in actual logic density, with Samsung in close second and TSMC at the third spot. As an added bonus, Samsung were pretty much the only ones actually using EUV until very recently. So when folks are shouting that Intel is ages behind TSMC, they're pretty much just demonstrating that they've not read any PDKs in recent years. The real issue plaguing most of these process nodes is thermal dissipation, while you can pack the transistors very densely, you can't actually get rid of the heat. So the end result is that you either have to decrease the dynamic performance of the device, or you have to space out the logic more or use intelligent placement and routing tools that account for power density on the die.

        So yeah, this is just marketing wank basically.

        • Wow, so informative.

          Meanwhile Intel can barely fab anything larger than 4c that isn't an FPGA on 10nm. TSMC has been fabbing on their 5nm process for some time now, and is poised to move to 4nm soon. Have you done a density comparison of TSMC N7 to Intel's 10nm+?

          https://semiwiki.com/forum/ind... [semiwiki.com]

          Also N7 was the first mass-produced 7nm node from TSMC. They've since release N7P and N7+ which are both more dense than N7. There's also N6 which is more dense than N7, not to speak of N5 and N5P . . . and wha

          • If you want to be at 7nm or 5nm, you pretty much have to buy an ASML EUV stepper [battleswarmblog.com].

            Are they still trying to do Cobalt for interconnects?

            • Yes and no, the current nodes seem to be possible with multiple patterning, I suspect it's also a question of parameters like die size, mask cost and other factors what's chosen for which process. And in terms of cobalt, maybe, there's a lot of talk about different solutions to the interconnect problem. Some folks are still sticking with aluminium, others are using copper and tungsten, etc. I suspect you'd have to pick the brain of a few folks at Lam to get any idea of what's the most likely candidate is go
          • My apologies for citing numbers from memory well past midnight. However, TSMC their 16 and 12 nm nodes are virtually identical and roughly equal to some earlier versions of Intel's 14 nm node in terms of electrical performance.

            But before we continue this discussion, you do realise all the publicly listed density numbers are for highly repetitive structures (e.g. SRAM, DRAM, ...), right? You cannot achieve that type of density with a complex non-repetitive interconnection pattern. Because if you're going

        • Re: (Score:2)

          by jabuzz ( 182671 )

          Maybe, but TSMC's 7nm is significantly better than Intels 14nm. While TSMC can deliver their 7nm in volume and have a 5nm delivering in volume Intel are still struggling to get any volume in their 10nm process. It is likely TSMC will deliver more 5nm this year than Intel has delivered 10nm in total.

          Also for the majority of processors Intel are on like 14nm++++ at the moment with a dodgy 10nm process which is years late and a 7nm process that is also late.

          • May I suggest you actually read up on an actual comparison between process nodes before you make statements like this? For practical complex logic devices Intel's 14 nm and TSMC's 7 nm process are virtually identical, for memory devices (where those theoretical density numbers are actually achieved) Samsung is the better choice ironically.

      • Re:2nm! 2! and the 6502 was 8um (Score:5, Informative)

        by kurkosdr ( 2378710 ) on Monday April 26, 2021 @05:45PM (#61317078)
        Keep in mind that TSMC measures in "planar equivalent" nanometers. Basically, when TSMC introduced their first FinFET (3D transistor) process, they compared the improved density offered by the new process to the one their then-current 20nm flat process offered and came up with a "planar equivalent" measurement of 16nm for the new FinFET process, despite the fact the new process was technically still a 20nm node. Intel measures in "true" nanometers, hence why their 10nm is actually a little denser to TSMC's 7nm (although they are thinking of going "planar equivalent" too, because lol marketing).

        In plain English, don't expect a 2nm feature in TSMC's 2nm node, so "2nm" is not as bad as it looks.

        Also, this means Moore's law isn't going to die when we reach the size of a couple of silicon atoms. It's just that fabs will make better and better use of the height dimension.
        • Stretching to height isn't done to fit more transistors in given area, it's done to better encircle the gate which makes the switching more efficient. Making transistors smaller effectively does the same thing - improves power efficiency. Because that's the true limitation, it's not useful to cram more transistors in a small area if power efficiency doesn't improve, because power is what the limiting factor is. Both from cooling side in desktops, servers, etc and battery life side for portables.

          • Making things smaller means you have a higher yield per wafer. A much higher one, as the defects in the wafer get less relevant.
            Assume you have a wafer that has only surface area for 4 chips. There are two defects spread out, making two chips unusable. Your yield is: tow working chips.
            Now reduce the size of the chips by a factor of 2. Now the same waver hosts 16 chips. 2 are defect. You yield is: 14 chips. That is 14 versus 2.

            • That's a nice theory, but in practice it seems to be outweighed by fact that smaller features are more susceptible to being ruined by tiniest imperfections. Or have you missed how much trouble Intel has been having getting beyond 14nm? Nodeshrink tanks yield and it's an uphill battle getting it back high enough to be viable. In relation to your example, you might only have two defects that are relevant for the larger node, but 20 or 200 that are relevant to the smaller node. That's kind of how you get nodes

        • Re: (Score:2)

          by djinn6 ( 1868030 )

          Also, this means Moore's law isn't going to die when we reach the size of a couple of silicon atoms. It's just that fabs will make better and better use of the height dimension.

          Does height really make a difference here? After a couple of layers, you'll have 10 nm gates 40 nm apart in height, which is not all that different from the same thing horizontally.

          Besides, even if the height can be effectively utilized, that just pushes Moore's Law back a bit. We're still stuck with 3D and can't really conjure up more dimensions.

    • Beyond nuts. Heisen-nuts with Schroedinger cats hidden around it. I do not see how it can work reliably at room temperatures. Quantum mechanics has no mercy.

    • Re:2nm! 2! and the 6502 was 8um (Score:5, Interesting)

      by Z80a ( 971949 ) on Monday April 26, 2021 @04:52PM (#61316916)

      The 6502 itself was nuts.
      A very usable and fast CPU in roughly 3500 transistors.

      • Re: (Score:3)

        by tlhIngan ( 30335 )

        The 6502 itself was nuts.
        A very usable and fast CPU in roughly 3500 transistors.

        6502 was not fast. It was usable, but that's because of the ISA similarities between the 6800, 6502 and Z80 processors to the point Microsoft could write a source code translator between them. Microsoft sold their translator and used it to port their software.

        What 6502 was is cheap. A 68000 (the 68k) chip cost $200. MOS technologies literally had a jar of 6502s and you could buy one and get the manual for it for $20. Remember MO

    • Process name do not correspond to physical dimensions. They are a metric of (digital) performance enhancement with respect to the previous generation. The minimum draw dimension is substantially larger than 2nm

  • Is that 2nm is about 200k atoms wide, roughly.
      Quantom effects may be a problem, not to mention electron migration.

  • TSMC will have 3nm and 4nm chips in 2022

    Meanwhile, Intel is still struggling with 10nm and their 7nm chips are delayed at least until 2022 [theverge.com]

    Intel is so behind they may never catch up.

    • Re: (Score:2)

      by pjrc ( 134994 )

      TSMC & Intel's "nanometer" aren't at all the same thing.

      https://hexus.net/tech/news/cp... [hexus.net]

      It's kind of like comparing cheap little computer speakers claiming to be 50 watts to normal a stereo system. They're just gaming the spec. You'd think more tech enthusiasts would take notice that chips claiming such different manufacturing specs have similar performance (Ryzen is faster but not massively so). It's a pretty effective marketing strategy.

      • Bullshit detected. Are you going to go on to claim that Intel's 10nm+, 10SF, or 10SFE are as dense as N7, N7P, or N7+? How about N6? Or N5/N5P for that matter?

        Go on, try it. "cheap little computer speakers" my ass. You really think Intel has a better or more-dense process?

  • They seem to have, maybe, gotten 10nm under control.

  • cores can a Threadripper have, if built on a 2nm process, assuming the same chip area as now?

    How fast will those cores run?

    When can I have one?

    • When one can afford it.

    • You may find out eventually. But I don't think AMD has planned that far ahead yet. They haven't even released Threadripper based on Zen3 yet, which presumably would still be N7. Zen4 (the next major update) will be N5 or N5P. AMD and everyone else will have to wait for Apple to get done with TSMC's latest nodes before they can buy any significant number of wafers.

  • And yet, graphics card are nowhere to be found, along with display drivers and other chips required by the auto industry.

  • 2nm unicorn farts (Score:5, Insightful)

    by hdyoung ( 5182939 ) on Monday April 26, 2021 @05:35PM (#61317058)
    The numbering has gotten ridiculous. Why dont they call it 1nm and then 0nm to complete the stupidity. A layperson sees 2nm and thinks wow, 4 times smaller than 8nm. Meanwhile the actual device differences are hardly even measureable when you put the devices next to Intel’s best in an electron microscope. Not saying that Intel isnt behind in tech, cause they are. But saying that TSMC is on a 2nm node and Intel is still on 10nm and hahah they so bad.... thats all marketing. Intel should rename their nodes just a equalize the perception mismatch. Marketing DOES matter.

    • Re: (Score:2)

      by AmiMoJo ( 196126 )

      Come on, Intel invented bullshit meaningless performance numbers.

      In any case, Intel parts are inefficient and can't compete on battery life. Whatever they call it, that's the reality.

    • Most people in the industry understand that it is not exact gate size. Calling it 2nm is better than "ultra mega small" which is not to be confused with "tiny extreme" of whatever some marketing person is going to do.

    • Intel's best, huh? lol. Okay. How much do you know about Intel's various 10nm processes? Are you aware that Intel was supposed to be mass-producing on 10nm in 2017?

  • Zero nm on the way (Score:4, Funny)

    by Tough Love ( 215404 ) on Monday April 26, 2021 @05:56PM (#61317104)

    After that, negative nm. Gets better and better.

  • Geo-Political Value (Score:5, Interesting)

    by ytene ( 4376651 ) on Monday April 26, 2021 @05:56PM (#61317108)
    Never mind what Intel and other global competitors think of this... what may become far more interesting and relevant in the medium term is China’s interests in Taiwan. China is expanding aggressively in to the South China Sea, converting coral shallows and reefs into islands and building bases.

    With China’s clearly stated view that Taiwan is merely a province/region of the nation state, I wonder what would happen if China were to make a forceful move to occupy Taiwan? Obviously the geopolitical fallout would be almost incalculably significant, but ultimately the longest term effects will come down to industries like semiconductors and companies like TSMC.

    I wonder what the effect would be on western technology companies - and the world economy in general - if TSMC were to be compromised geo-politically?

    • If China pulled some shit concerning Taiwan, the entire West would blow China back into the stone age. You don't fuck with people's mission critical industries lightly. That's why China will keep its mouth shut about Taiwan for the next ever. They're not stupid enough to do something about it. Besides, the US and Europe have been making it increasingly clear that Taiwan is not a part of China for the last decade and China hasn't said shit. We've also told Taiwan to shut up about China being theirs a few tim

      • Re: (Score:2)

        by vlad30 ( 44644 )
        More likely the west will start to move critical manufacturing back to where they can be protected and china will stay quiet until they they think they can take Taiwan without a fight. Although the noise they are making they believe they can win a fight now and those factories are very useful particularly if they are not allowed to buy the chips

    • Re: (Score:1)

      by kokojie ( 915449 )
      There wasn't really any geopolitical fallout when Russia annexed Crimea, and is about the annex Ukraine. I don't really see anything happening if China annex Taiwan, as they have a strong claim over Taiwan, and they are way stronger than Russia.

    • I wonder what would happen if China were to make a forceful move to occupy Taiwan?

      one interesting option, provided here long ago by another /.er, was to provide all Hong Kong residents an accelerated path to citizenship in the US / UK.

      argument goes: lotta talent there, lots of their values align with ours, and they'd appreciate the cheaper real estate, ha.

      would be interesting to adopt that for the taiwanese, as well.

  • why ads as articles on slashdot (Score:3)

    by iggymanz ( 596061 ) on Monday April 26, 2021 @06:15PM (#61317152)

    This was full of marketing and hype crap, not technical news.

    Can we get this shit off this site? How does it get approved?

    • Re: (Score:2)

      by bugi ( 8479 )

      not technical news

      I appreciate the defogging I get from the /.crowd turning PR-speak into technical news. I don't live close to the chip anymore, so I've lost my ability to compare TSMC nm to Intel nm, other than the general knowledge that they aren't 1:1. Thanks to kurkosdr, at least now I know it's "planar equivalent" and that Intel might adopt the same measure.

      • But there are better articles that focus and educate on such matters, this article was 80% marketing and investor hyping spew. Even that "planar equivalent" statement has all kinds of exceptions and nuances.

        • Re: (Score:2)

          by bugi ( 8479 )
          That's also very useful info. Do you by chance have an article to recommend?

  • A German researcher has measured transistors used in L1 cache, Intel 14nm+++ vs TSMC 7nm (AMD Zen)

    Findings were:

    Intel 14nm++ transistor size: 24x24nm
    TSMC 7nm: 22x22nm

    Now, of course there is a difference and of course things till go smaller, as they progress, but the difference is nowhere where one would have expected it, based on the names.

    Things might change once Intel gets into fab business (they will be forced to claim faux figures)

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