Exploring the Open Source That Really Goes Into a RISC-V Chip (hackaday.com) 32
"Maker Andreas Spiess talks about the Open Source that really goes into a RISC-V chip and the ESP32-C3," writes
Slashdot reader nickwinlund77 — sharing a link to this article from Hackaday:
It's an exciting time in the world of microprocessors, as the long-held promise of devices with open-source RISC-V cores is coming to fruition. Finally we might be about to see open-source from the silicon to the user interface, or so goes the optimistic promise. In fact the real story is considerably more complex than that, and it's a topic [Andreas Speiss] explores in a video that looks at the issue with a wide lens...
nickwinlund77 writes: The YouTube video starts out with a good general history of competition between large businesses over architectures and embracing the standards for tech which many of us have depended on throughout the years. The video then gets into the technical specifics of the ESP32-C3.
Hackaday adds: His conclusion is that while a truly open-source RISC-V chip is entirely possible (as demonstrated with a cameo Superconference badge appearance), the importance of the RISC-V ISA is in its likely emergence as a heavyweight counterbalance to ARM's dominance in the sector.
nickwinlund77 writes: The YouTube video starts out with a good general history of competition between large businesses over architectures and embracing the standards for tech which many of us have depended on throughout the years. The video then gets into the technical specifics of the ESP32-C3.
Hackaday adds: His conclusion is that while a truly open-source RISC-V chip is entirely possible (as demonstrated with a cameo Superconference badge appearance), the importance of the RISC-V ISA is in its likely emergence as a heavyweight counterbalance to ARM's dominance in the sector.
The real problem is the fab. (Score:1)
If I can only buy implentations that are either
* fast, but made in billion-dollar fabs, where the actual chip is still somehow monopolized for the purposes of artificial scarcity, while the fab is not trustworthy anyway (like a Chinese fab with NSA and Mossad and FSB moles putting in backdoors on top of the Chinese ones), or
* truly openly manufactured, but in ancient fabs or with some home etching toys, slow as hell, and still cost an arm and a leg,
then an open source hardware standard is really just a non-
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* fast, but made in billion-dollar fabs
A key point here is that you have a choice of billion-dollar fabs. Both TSMC and Samsung offer state-of-the-art fabbing-as-a-service. So neither can charge a monopoly premium.
The world would benefit from a 3rd provider. As the world shifts away from x86 and toward RISC-V and/or ARM, Intel may end up with spare capacity and offer FAAS as well.
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Intel has put a bunch of money into SiFive, make your own predictions from that...
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Intel has put a bunch of money into SiFive, make your own predictions from that...
Based on that, my prediction is that SiFive will turn out to be a dud.
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How much does it cost to fabricate a basic RISC-V chip at 7nm?
That depends on volume and die size.
Figure $200M in design costs and masking. Then about $3 per mm^2 for actual fabbing.
A RISC-V is 30 mm^2 at 28 nm, so let's assume it uses 1/16th of that at 7nm. So that is about 2 mm^2.
If you are only making a million, it is going to be hecka expensive. $206 for a 2mm chip.
If you are making a billion, they will cost $6.20 each.
Disclaimer: These numbers may be wrong.
Re: The real problem is the fab. (Score:3)
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Where do you get 3$ per mm2?
From a 30 second Google search.
just that the rule we went by was 0.10$/mm2.
That may be the cost of the silicon wafer. But you will pay much more to have it fabbed to ICs in a 7nm facility.
The cost per unit area is less in an older fab.
But, as I said, my numbers may be way off. Please don't rely on them for your $200 million project.
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RISC-V allows edu & small business to design C (Score:5, Interesting)
We are seeing a bit of variety in micro-controllers, and small SoCs that many small businesses use in their products. However, almost all these products have extra hardware that is not always needed. In some cases taking a little power. Image a SoC designed with zero extra hardware, tuned for a specific application and targeted for a certain battery life. Apple, Samsung and many other HUGE & Large business can afford to make their own targeted SoCs. But soon, even medium businesses would be able to do so. Eventually, even small businesses that produce misc. home, play, vehicle and office products that use processors can take advantage of open source hardware.
In addition, having an open CPU arch. allows educators to show design elements without violating copyrights, patents, and getting sued because of those violations. It would have been nice if ARM, AMD or Intel had an education program in CPU design.
But, seeing how badly Intel implemented certain design elements, (speculative execution comes directly to mind), I suspect those in education would have called out Intel security flaws within 1 year. Publicly. We, on the outside, would have eventually gotten a more secure product out of that process. But, in the mean time, Intel would have chosen to sue the living *ell out of the education institute that brought that security nightmare to light. Even if Intel did not have a chance at winning, they would not have simply bent over, and took it.
Will RISC-V change to the world?
No.
Can RISC-V improve the status quo?
Yes.
Could we see more open hardware over the next few years?
Of course, (but who listens to me?).
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The real power of RISC-V is that it allows businesses to design, have manufactured and use their own processors for application specific purposes. Instead of having to depend on other companies to sell products that only come close to meeting their needs.
We are seeing a bit of variety in micro-controllers, and small SoCs that many small businesses use in their products. However, almost all these products have extra hardware that is not always needed. In some cases taking a little power. Imagine a SoC designed with zero extra hardware, tuned for a specific application and targeted for a certain battery life. Apple, Samsung and many other HUGE & Large business can afford to make their own targeted SoCs. But soon, even medium businesses would be able to do so. Eventually, even small businesses that produce misc. home, play, vehicle and office products that use processors can take advantage of open source hardware.
We design, have manufactured, and use our own processors for all sorts of application specific purposes (hence the term ASIC).
We do more digital these days than analog, but we still have plenty of mixed signal going on.
The team size has varied considerably over the years, but we typically do both front+back end with 4-8 people for one chip, sometimes packaging and test as well. For long established products the teams get a lot larger.
The big expenses (not necessarily in order) are:
1) licenses
2) engineering
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Some other processor architectures are open to some degree too, sparc and power for instance. Not sure what the current status is with architectures like alpha and m68k etc, there is at least one company that has created an updated m68k implementation on an fpga to run old amiga and atari software.
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there is at least one company that has created an updated m68k implementation on an fpga to run old amiga and atari software.
There is also an excellent open source alternative: the MiSTer project [github.com].
The list of computers, consoles, arcade machines and other things they have FPGA cores for is on the bottom of the column on the right of the page, it goes from the EDSAC and PDP-1 over the 8-bitters to the i486 PC, Mac Plus, Amiga, ST and Archimedes.
Cores in the works, such as Playstation, are not yet in the list.
Fake open source (Score:2)
Due to the fact that they allow proprietary extensions, RISC V is a recipe for CPU fragmentation and even worse weâ(TM)ll end up back in an ARM situation.
They really should make the CPU architecture requirement that it be open like how the GPL is open. Any changes or additions should be open.
Also, we need an open source GPU. Is anyone working on that with any level of seriousness?
RISC-V Extensions are Open too (Score:4, Informative)
You misunderstood how the RISC-V extensions work.
RISC-V defines a base ISA that every processor must have (at least, if said microprocessor is to be called RISC-V). Then there are a bunch of extensions, that each and every entity implementing RISC-V may or may not include in the processor, according to their needs. But all of these extensions are Open too. And standarized.
To give you an example: Alice, Bob and Claire are working on Three different RISC-V microprocessors. The three microprocesors must have the base instructions. Claire decides that she does not need SIMD, while Alice and Bob decide to add SIMD, then, by virtue of of the way RISC-V handles this, the SIMD instructions of Alice's and Bob's have to be the same.
Meanwhile, Bob decides that he does not need Virtualization support, while Alice and Claire do want it. Again, the Virtualization extension has to be the same in both Alice's and Claire's microprocessor.
Yes, this may lead to fragmentation, no different than with intel, in which certain things like Virtualization are present in some processors and not in others, or like transactional meory only be present on Xeons.
I guess that, when the time comes to move RISC-V beyond embeded, into client and server territory, then a group will come to standarize what parts of the ISA that until that point were "Extensions" are now needed.
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Due to the fact that they allow proprietary extensions, RISC V is a recipe for CPU fragmentation and even worse weâ(TM)ll end up back in an ARM situation.
This absolutely is open source hardware, you're just confusing "Open Source" with "Free Hardware" (like Free Software).
They really should make the CPU architecture requirement that it be open like how the GPL is open.
Why? RISC-V permissively licensed. There's nothing to stop you from adding something of value to it, licensing that derivative work under GPL-like restrictions and then anybody who wants to use the thing you created would have to then abide by those license terms.
Also, we need an open source GPU. Is anyone working on that with any level of seriousness?
I think you should get your terminology right, based on the above you probably want a "Free Hardware" GPU, Open Source would cert
A Processor is only part of the equation (Score:5, Interesting)
You need also a memory controller, a GPU, various bus controllers and various differnt kinds of networks.
Do not missunderstand me, RISC-V is a giant leap in the right direction, but we are far from the finish line.
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Comment removed (Score:3)
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Maybe, just do both [abopen.com]?
Others [abopen.com], like Open POWER, seem to be screaming "Hey! Look at me!" and wondering why the new kid on the block is getting all the attention.
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People focus on the "open/free" part of it, but SPARC seems about as free.
It's GPL'd, that might be attractive to some people but not to the majority of would-be contributors. If you have an FSF mindset then absolutely SPARC is the better choice but most of the people doing the work aren't particularly concerned with that.
All architectures have issues but SPARC has some particularly annoying things like Delay Slots and Register Windows, both things were good ideas and optimizations at the time. For example before branch prediction, speculative execution and highly threaded workfl
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IIRC, SPARC required expensive membership dues to the SPARC Foundation.
Re:jeey (Score:4, Funny)
Hey... My pussy gets so wet
Perhaps, but that isn't the open hardware that we're talking about right now.
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That's not hardware, it's wetware. And it's not just open, it's open sores.
A RISC-roll (Score:3)
I'm truly ashamed...