Cerebras Systems Unveils a Record 1.2 Trillion Transistor Chip For AI (venturebeat.com) 67
An anonymous reader quotes a report from VentureBeat: New artificial intelligence company Cerebras Systems is unveiling the largest semiconductor chip ever built. The Cerebras Wafer Scale Engine has 1.2 trillion transistors, the basic on-off electronic switches that are the building blocks of silicon chips. Intel's first 4004 processor in 1971 had 2,300 transistors, and a recent Advanced Micro Devices processor has 32 billion transistors. Samsung has actually built a flash memory chip, the eUFS, with 2 trillion transistors. But the Cerebras chip is built for processing, and it boasts 400,000 cores on 42,225 square millimeters. It is 56.7 times larger than the largest Nvidia graphics processing unit, which measures 815 square millimeters and 21.1 billion transistors. The WSE also contains 3,000 times more high-speed, on-chip memory and has 10,000 times more memory bandwidth.
Cough, cough "SkyNet" cough, cough (Score:2)
It's now only a matter of time...
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They need to stop using the word "AI" altogether. Those two letters get the kooks in a frenzy, and there are more than enough that are very unhinged and might try to attack the people or the places making this stuff.
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Oh God, please tell me you are not one of those "AI is going to kill us all!" kooks.
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"AI" isn't even at the level of a housefly in terms of 'smarts', and despite the hype, there has been very little progression since then "Eliza" days of the 1970s and now, in terms of said smarts.
Either we are going to be dealing with profoundly retarded Terminators, or this crap is never going to happen because it's sci-fi fantasy. I'm putting my money on the latter.
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"there has been very little progression since then "Eliza" days of the 1970s and now, in terms of said smarts.."
I hate it when I mangle a sentence
"There has been very little progression between the "Eliza" days of the 1970s and now, in terms of said smarts."
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"AI" isn't even at the level of a housefly in terms of 'smarts', and despite the hype, there has been very little progression since then "Eliza" days of the 1970s and now, in terms of said smarts.
That DOES put current AI ahead of the average flat earther... which doesn't reflect well on where humanity is headed.
Either we are going to be dealing with profoundly retarded Terminators, or this crap is never going to happen because it's sci-fi fantasy. I'm putting my money on the latter.
By the time we have terminators, the average human will be so retarded that the terminators will appear to be geniuses. They won't need to be particularly smart to win. Odds are however that the idiocracy will bring down society long before the singularity happens.
I call bullshit. (Score:1, Informative)
I call bullshit on that one.
They claim a 42,225 mm^2.
That's over 4 dm^2, a rectangle 20 cm x 20 cm, roughly 7 in x 7 in.
And the biggest available wafer only sports 64,000 mm^2. [wikipedia.org]
So it cannot be a single chip. Now they may packages a bunch of smaller chips into a single package, but that's been done before and is much less impressive. It cannot be the largest chip ever built. Possibly the largest number of chips in a single package, but they lost all cred at this stage.
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They claim a 42,225 mm^2..... And the biggest available wafer only sports 64,000 mm^2. [wikipedia.org]
Now, last I checked, 42,2215 is less than 64,000. Not sure I see the problem?
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The only issue aside from needing perfection is a fault-tolerant design with redundancy.
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This article seems to indicate that there are other limitations that indicate your likelihood of getting *any successful chips would be quite low...
https://www.quora.com/Why-does... [quora.com]
"Perfection impacts yield" is generally acceptable because a given wafer can produce numerous die so getting some(hopefully high) % success is just a cost factor. When you need nearly your entire wafer to make a single die And your % success is negatively affected by the size of the die itself you're shooting yourself in the foot
I call math error, lol. (Score:2)
SQRT(42225) is 205.487, or 200mm on a side.
A wafer is over 300mm these days at the big foundries, so quite doable.
Those kind of metric conversions have crashed spacecraft, so I wouldn't feel too bad. :)
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That's what he said. 200mm = 20cm ~= 7in.
It'll fit on a wafer, but it won't have much room for error.
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It's possible, albeit expensive, to stitch multiple mask images together at the wafer level by careful projection and position control. That's how large field camera chips are made. 36x24 mm doesn't fit otherwise. Wafer-sized chips are also made for x-ray detection applications.
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I didn't say I'd fit one chip on a wafer, I said that Grog6 is calling math error and yet coming up with the same numbers.
Possible but will have architecture/power issues (Score:2)
If it's a square chip, then the corners are going to be outside the disk of the 64k mm^2 wafer but who says it has to be square?
Where I see the issues is when we talk about interconnects between the cores? A little more information like the size of the cores on the chips as well as more explaining the core interconnect strategy would be nice. How many other cores (and memory) does each core connect to. Then, of course, there is power distribution and dissipation for the chip.
If it is what they say it is,
Re:I call bullshit. (Score:5, Informative)
Re: I call bullshit. (Score:1)
Re: I call bullshit. (Score:2)
It's not bullshit (Score:5, Informative)
Most modern process technologies run on either 12" or 18" wafers. I don't know what the wafer map looks like and I'm too lazy to do the geometry, but it may literally be one die off a wafer at that size.
The things that would concern me personally as a former lead ASIC designer are:
- Design - over that kind of silicon area, how many possible clock domains and PLLs do they have? There'd have to be a lot of clock domains asynchronously latching data because even at low speeds you'd have enough clock skew to choke a blue whale. And what tool could actually place and route and what kind of memory/CPU did it have? How was power and signal integrity closed at this scale as well? And what type of front-end and back-end back-annotated simulation did they conduct, or was this all reliant on formal verification + static timing analysis? I'm even curious how long physical design and design-rule checks took on this.
- Testability - in several respects, this is a monster to test, so how long does scan/BIST/memBIST take to run, what kind of probe card and load board was designed to test this at "wafer sort" (and I use that term loosely), and how do they deal with things like gross IDD (i.e. dead shorts between power and ground)? I get that they have some kind of built-in self-repair, but one gross IDD failure and you're literally cooked. Yields must be utterly dreadful even with a stable process at a Tier 1 fab.
- Packaging - again in several respects, including how was the packaging designed, what type of I/O and power distribution scheme was used (at 15kW no less!). I'd also be really concerned about what type of heat dissipation at that much power they have, and how they prevent warping of the package substrate because of thermal differences across the area of the die/package. Is this even possible with FR4 or did they go to PTFE or some other material? Same with once it's placed on a board.
- Product - what kind of I/O is this thing supporting? How many layers of PCB did they use for this? What actually feeds this thing data coherently? Where does it all go?
Bluntly, that's a lot of questions. The fact that nobody heard anything about this up to now may be a factor of NDAs, but this monstrosity is so beyond the pale from a design perspective that I don't know that I could take someone seriously if they even told me to work on this. Again, I'm not saying it's impossible, but I'm saying that truly nothing like this has ever been attempted, and I would be much more reliant on a subdivided design with fast interconnect even when they're talking about the type of computing problem they're trying to solve. Let's see the package alone, and it'll answer some more questions for us.
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Since this is a "Sparse Array" device it may be possible that they plan on selling devices graded on how many quadrants are properly functioning, and merely marking or deactivating those bad cells/cores that were found to have problems during testing. I understand companies like Intel will crank up the GHz during testing and scale the frequency back until the chip passes the test, and the part is then labeled and sold for use at that GHz processing speed. Other types of failures just wind up on the recycle
Silicon penis waving? (Score:2)
And what does it matter that it's single wafer vs multiple separate dies?
Do kids typically complain when mom buys Dino Bites instead of Fruity Pebbles?
At least separate dies can be connected in 3D, reducing the length of the signal path and (theoretically) getting a much better throughput between dies.
This is it! (Score:2)
They finally built a chip that can run Crysis! ;)
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Windows 12 beta has already bogged it down to a crawl.
WSI (Score:3)
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what's a "wsi" ? wafer sized ic ?
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wafer scale integration
google it
or use wikipedia
or imagination
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Wafer Scale Integration
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Imagine (Score:2, Funny)
"My God, it's full of waffles!" [Re:Imagine] (Score:2)
It is a cluster! [bbc.com]
Maybe they couldn't figure out how to separate the chips off a wafer, so left them in place and rebranded it as "the biggest chip ever".
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815 sq mm (Score:2)
"...which measures 815 square millimeters..."
So, it's roughly the side of a side salad plate? Better be chilled.
Re: 815 sq mm (Score:2)
Well crap. I'm dumb. It's a bit larger than a sq inch.
Goodnight internet.
At least you caught it. (Score:2)
look above, lol.
Who cares about the number of cores? (Score:2)
For a system this size, the interconnect architecture is much more critical than the sheer number of cores. Anyone know what's going on there?
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Re: Who cares about the number of cores? (Score:2)
Anyone know what's going on there?
Lots of parallelism and likely nothing that can't be achieved using commodity hardware for far fewer dollars and watts.
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The energy cost of communication in this architecture is well under 1 picojoule per bit, which is nearly two orders of magnitude lower than in graphics processing units
The collection of core-local memory aboard the WSE delivers an aggregate of 9 petabytes per second of memory bandwidth â" 3,000 times more on-chip memory and 10,000 times more memory bandwidth than the leading graphics processing unit
Perhaps not?!
Re:Who cares about the number of cores? (Score:4, Insightful)
Why don't you read the article? There is a whole section dedicated to the interconnect.
This is going to be an expensive chip. (Score:3)
The bigger it is makes the odds of a catastrophic defect more likely.
That's why bigger chips are more expensive, because they have to throw so many away.
The basic silicon is relatively cheap; but by the time you put 18 layers of diffusions, metal layers, and oxide layers on it to fine linewidths, it's pricer than platinum.
Bondwires are made of gold, so think of the relation there. :)
This is probably a $5million chip, and I'm likely to be off by more than one zero. :)
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Plus, after you've made the thing, you need to come up with some way to keep it from catching on fire when you're using it. Something that size is going to run some serious wattage that you need to get out, and it's got to be running up on some serious challenges to get all that wattage out even with that big of a chip.
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While that's true not all chips are created equal, it also depends on how many parts of the chip are critical and how much can be gated off as defective. For example GPUs often have versions with some SP/ROPs disabled. If this is an all-compute chip with a huge array of identical compute blocks that could be easier than a GPU with unique elements like display outputs and such.
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Probably.
I've seen systems built with $30,000 FPGAs (that's $30,000 EACH in 1000 piece quantities!). They were fairly large chips already (the package was around 8cm x 8cm, but the die is relatively small comparatively).. The system had 4 of them in most configurations, though I think we had one with two boards, so 8 of those FPGAs (think of it - nearly a quarter million dollars in FPGAs).
Given the size of this chip, it wil
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The article says, however (emphasis mine):
If you have only one chip on a wafer, the chance it will have impurities is 100%, and the impurities would disable the chip. But Cerebras has designed its chip to be redundant, so one impurity won’t disable the whole chip.
I'm pretty sure by "one" they mean "a few". Of course there are almost certainly some critical areas where defects might make the whole cihp fail, but probably it is tolerant to a big portion of the defects. Even without defects, this will certainly not be a cheap chip, as a whole wafer for typical CPUs costs somewhere around $10,000 or more, depending on the process used, and any more specific techniques can of course drive the prices up significantly (and those ty
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A defect may take out a portion of the chip, but the remainder should be configurable for use. With 10^5 cores and an inter-processor communication "fabric" (their term), you should be able to reconfigure or reroute around the damaged area.
I expect that, much like with microprocessors, they intend to bin these chips/wafers according to how many defects they have and how well they perform at the wafer-scale testing. That is, the wafe
These Guys Should Build A Monster GPU! (Score:3)
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So, you imagined something that doesn't exist. Then call plans and products of companies making money "BS".
Then say you wish you had cool gaming rig gizmo.
yup, you're a kid.
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I could then play Civ 6.
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Hmm. Maybe you need to go show Nvidia and AMD how it's done? Don't you think that if it was that easy, that someone with the resources of Intel wouldn't have been doing it in order to gain market share? No - instead you see Nvidia and AMD slugging it out with modest gains because as it turns out, doing that kind of processing massively faster is really fucking hard without making other unacceptable compromises. Like having multiple power supplies in your system to power up some mammoth processing engine
Re: These Guys Should Build A Monster GPU! (Score:2)
Remember how we all thought in the 1980s that by 2020 or so we'd have "VR that looks like real life"?
No; most people had never even heard of "Vee Argh" in the 80's until Lawnmower Man came out. Anyone weened on Gibson (or Stephenson's Snowcrash) were familiar with the concept, but it wasn't until after the 90's that we began to do more than hope.
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You should learn about Physics. Moore's Law is dead, despite best efforts. You just never noticed.
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Moore's law says nothing more than that the number of transistors on an integrated circuit doubles every two years.
While log-plot the curve for mainstream CPUs has bent a little flatter over the past 10 years, this chip with over 1e12 transistors puts a dot solidly on or even above the original main line going back to the 1960s.
In other words, Moore's law isn't dead quite yet.
rigid temple of the moist oracle (Score:2)
Moore's mildly favoured formulation chose to couch it in those terms.
In addition to his having been inside the loop enough to get first dibs on a new economic paradigm of sustained exponential growth, Moore was canny enough to choose the formulation with maximal wiggle room (so as to gather more credit, while risking less blame). Many high school students are equally canny. This is not the toga
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It doesn't matter: He said what he said.
If you really dislike it so much, you can promulgate your own law.
3dfx throwback (Score:2)
I don't know why, but whenever ibsee posts like this, i always think of those old 3dfx commercials, where they do this magestic dream, of using their tech to solve the worlds biggest problems, then throw in the "wait a minute... we could use this to play games!" :)
Where are the pics of this mega-chip? (Score:2)
Pics or it didn't happen!
The Good Part (Score:2)
Chip or wafer? (Score:3)
The article makes it clear that this device is a wafer and not a chip, even though the title still makes claims about a chip. The wafer-scale device is still potentially impressive, but the claims of chip-level size and transistor count are misleading.
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The article makes it clear that this device is a wafer and not a chip, even though the title still makes claims about a chip.
It's both. It's a chip the size of a full wafer, instead of one of many chips cut out of a wafer.
closed-kimono orgasmic gush (Score:2)
I read the fine article. Typical closed-kimono orgasmic gush.
While I didn't actually learn anything much at all, the penny finally did drop on Master Sergeant Schultz's likely career trajectory after the war concluded.
IEEE Spectrum (Score:2)