Samsung Chips Will Get Faster and Easier on Your Battery in 2020 (cnet.com) 41
Processor progress is harder to come by these days, but Samsung says it'll build chips next year that will give you a bit more battery life or a little more speed. From a report: Through improvements charted by Moore's Law, chip electronic components called transistors get steadily smaller. On Monday, Samsung said it's taken the next step along the Moore's Law path, shrinking a transistor measurement to 5 billionths of a meter -- 5nm -- from 7nm. To get some idea of just how teensy that is, about 2,000 would fit end to end across the width of a human hair. The new petite size means the Korean company will be able to add more electronic abilities to its chips. It also means the chips will get either a 10% speed boost or a 20% savings in power. The development could help not only Samsung, which builds the Exynos processor for its own phones, but also Qualcomm and other companies that rely on Samsung's foundry business to build their chips.
Removable batteries? (Score:2, Interesting)
Re: (Score:1)
Re: (Score:2)
Don't worry, in another ten generations of product releases, the batteries will last at least twice as long as the product ever will ;)
Extrapolating the rate of deterioration in consumer appliance and device reliability from the past four decades forward, that will happen even with zero improvement in battery technology.
Re: (Score:2)
> Don't worry, in another ten generations of product releases, the batteries will last at least twice as long as the product ever will ;)
These energy efficient chips will allow phone manufacturers to create even thinner batteries. These ultra thin batteries will need to work even harder and go through ever more charging cycles decreasing the life of the battery and ultimately the run-time of the phone.
The problem isn't the CPU (Score:5, Insightful)
The problem isn't the CPU. The problem is all the Apps that insist on running constantly in the background, using GPS and other tracking sensors to spy on you.
I have a Moto G4 and I couldn't figure out why the battery was only lasting 6-8 hours. One day I finally quit Facebook and uninstalled the Apps for Facebook and Messenger, and voila! Now I get 24+ hours of battery life easily.
Get app developers under control and you get battery usage under control.
Re: (Score:2)
Re: (Score:1)
I am currently running Lineage on the G4 but it is no longer supported it seems. I also have a Moto G6 running AOSP 9.0 Treble and an old OPO still on Lineage OS, not sure which version... The OPO was a really promising phone except for the cheap radio they put in it that doesn't do many LTE bands.
When I switched to Ting I had to get the Moto because the OPO can't pick up T-Mobile anywhere.
Re: (Score:2)
I've scanned my devices and do not believe my network is compromised but I'm far from an expert.
Re: (Score:2)
You talk about spying and then mention apps which have core features that rely heavily on push notifications / constant server connections, and despite your assertion imagine a world where you could get the functionality you clearly voluntarily used AND get good battery life.
In other news, I turned my smartphone dumb and I get much better battery life now!
Chips should be faster (Score:1)
5nm is NOT a true process (Score:4, Informative)
5nm, of course, is just a tweak of the 7nm process- where only certain chip elements have the smaller size. The power and or clock improvements are real.
Samsung competes with TSMC, which has its 7mn+ process coming later this year to same effect.
The real story is not this nonsense, but the issue of EUV (use of ultra-violet wavelengths with masks) and possibly larger wafers. Both these techs have been delayed for a decade now, cos of fundamental issues. Intel has crashed and burnt over both, having now the WORST process tech amongst the giants.
EUV is currently used as little as possible, and only on layers where trad wavelengths can no longer be forced to give improvements. No fab has proven the feasibility of going full UV, even after 15 years of research in this area by the tool makers.
Current 7nm has two tweaks available for minor improvement- and this article talks of one of these tweaks. After both tweaks have been rolled out, a wholly new process is going to prove to be insanely expensive and difficult, and is probably FIVE to ten years out.
AMD's answer is CHIPLETS- lots of smaller chips sitting on the same substrate- so a 'chip' is improved by using more chiplets. AMD's new Zen2/Ryzen 3 release in a few months time is a chiplet design, where 4 chiplets (CPU or GPU clusters) can sit around the same I/O chiplet.
PS as process shrinks finally end (we don't know how many more we have left, but they will have exponentially longer gaps between each new process to come), there is another option. Circuit improvement. Current circuits are usually sub-optimal, being cheaply placed by very poor chip CAD software that is designed to make the chip design process EASY, not good or efficient.
By allowing far better CAD algorithms, of Human input from 1st class Human circuit designers, a current process could probably see a 2-5 times improvement in many areas. With a tweaked 7nm being around for maybe as long as 10+ years in the worst outcome, there is loads of opportunity for superior circuit design to provide significant improvements (the very reason Apple now designs its own chips).
Re: (Score:3)
By allowing far better CAD algorithms, of Human input from 1st class Human circuit designers, a current process could probably see a 2-5 times improvement in many areas. With a tweaked 7nm being around for maybe as long as 10+ years in the worst outcome, there is loads of opportunity for superior circuit design to provide significant improvements (the very reason Apple now designs its own chips).
I call bullshit on this last part. If there was a 2-5x speed improvement to be had by optimising by human experts we would be having those. I mean how many experts in the world would we need? There's only a few major players in this market and I guarantee you they aren't mashing the autoroute key and calling it a day.
Re: (Score:2)
"If there was a 2-5x speed improvement to be had by optimising by human experts we would be having those. "
Except when the next process was coming in two years, you work on that because it halves your marignal cost so you never get the opportunity to do the one-time non-recurring engineering for design and process improvements. For the lead vehicle on an Intel process, for example, there was typically less than 1Q to tape-in once test chip data was available.
You can't choose to slow down to do that work bec
Re: (Score:2)
AMD's answer is CHIPLETS- lots of smaller chips sitting on the same substrate- so a 'chip' is improved by using more chiplets.
Chiplets are not an alternative to using a smaller process. They don't make your processor any faster or more efficient. A chip made up of chiplets doesn't work any better than a single larger chip.
There are two reasons that chiplets are useful. One is that you can mix different processes. Use a very expensive 7nm process for the performance critical parts of the chip, and a cheaper 12nm process for the parts that don't matter that much. The other is that it helps your yields. If you split a big chip
Marketing and manufacturing capability.. (Score:5, Informative)
The quoted manufacturing capability is no longer accurate. It is now artificial. Back in the day, a 65nm process was indicative of a manufacturing process that could create features with a minimum pitch of 65nm. Then people started to create FinFET transistors - a process that allows for denser transistors. But how to sell such a process? The answer is to call it a 0.6*65nm process -- when it is actually still a 65nm process. The idea is that the new FinFET transistors result in the same transistor density that would have been achieved with traditional transistors and a 0.6*65nm process.
So the quoted pitch is now an indicator of transistor density -- sort of. Marketing also has a say so one should not read too much into it. Smaller is better but only for the same fab. It is not a good metric for comparison between fabs.
NOTE: The 65nm and 0.6 numbers are just for this example. Actual values will differ. I believe 14nm parts use a 22nm process - but one should verify if you want exact numbers.
Re: (Score:2)
Can we get small phones again? (Score:1)
The consumer wants tablet sized phones is a lie. Phones got bigger because there is no space for a battery that can keep alive a modern processor for a day.
I disagee. And I agree. (Score:1)
My main beef is with tiny keyboards and buttons. Much smaller than a human finger. And resulting cancers like autocorrect.
My second beef is the lack of information displayable at the same time.
And my third beef is phones so large that I can't hold one and type with the same hand, and that it does not fit in my damn pocket!
While being pointlessly thin.
I already buy thick rugged phones (Thanks Shenzen!), so breakage and battery life are no issues for me.
And I *hate* folding phones!
Flip phones already were ann
5 nm node doesn't mean 5 nm transistors (Score:2)
From TFS: "shrinking a transistor measurement to ... 5 nm -- from 7nm."
These node names have long lost their correspondence to actual dimensions on a chip. For 7 nm (easier to find data on than 5 nm) the transistor density is 60-80 transistors per square m, about 120 nm for a square transistors.
Source: https://en.m.wikipedia.org/wik... [wikipedia.org]
Re: (Score:2)
And don't forget 3d / layering. Even 14nm is more compact than 5nm if you layer it twice. The whole slashvertisement is amateur hour.
If the measurements are actually 14nm and 5nm (not market-speak that approximates them), you'd actually need 8 layers of 14nm to surpass one layer of 5nm. You get almost 8x as many 25nm^2 (5x5) features in an area of 196 nm^2 (14x14).
Re: (Score:1)
... a human red blood cell is typically less than 10 um in diameter at the widest point.
In other words you could lay approximately 50 human red blood cells end-to-end along a single 5 nm transistor.
1 micrometer is 1000 nanometers, so a blood cell 8 um in diameter [genomesize.com] would be 1600 times as wide as a 5-nm transistor (if a 5-nm transistor were actually 5 nm in width).
Rubbish reporting (Score:2)
Any self respecting geek knows that the 5nm process node name bears hardly any relation to transistor dimensions, or any other dimension. In fact, the spacing between metal traces in Samsung's so-called 5nm process is somewhere around 32nm, the public not really knowing for sure because Samsung has not yet released details of this node.
The real news is, the near-complete break with deep UV in favor of EUV. And as we all know (right?) EUV photolithography is still not ready for prime time. Last I heard, ther