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Samsung Starts Mass Producing Industry's First 10-Nanometer Class DRAM (engadget.com) 43

Posted by BeauHD from the smaller-and-smaller dept.
An anonymous reader writes: Samsung is now mass producing the industry's first 10-nanometer class, 8Gb DDR4 DRAM chips, ahead of competitors SK Hynix and Micron. It will produce 10nm-class DDR4 DRAM modules this year varying from 4GB for laptops and up to 128GB for enterprise servers. Samsung also promised to reveal 10-nanometer-class mobile DRAM "in the near future." The announcement marks a big milestone for the company after it first mass produced 20-nanometer-class 4GB DDR3 DRAM chips in 2014. "Samsung's 10nm-class DRAM will enable the highest level of investment efficiency in IT systems, thereby becoming a new growth engine for the global memory industry," said Young-Hyun Jun, President of Memory Business, Samsung Electronics. "In the near future, we will also launch next-generation, 10nm-class mobile DRAM products with high densities to help mobile manufacturers develop even more innovative products that add to the convenience of mobile device users."
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Samsung Starts Mass Producing Industry's First 10-Nanometer Class DRAM More

Samsung Starts Mass Producing Industry's First 10-Nanometer Class DRAM

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  • A SIMM, or single in-line memory module, is a type of memory module containing random-access memory used in computers from the early 1980s to the late 1990s. It differs from a dual in-line memory module (DIMM), the most predominant form of memory module today, in that the contacts on a SIMM are redundant on both sides of the module. SIMMs were standardised under the JEDEC JESD-21C standard.

    https://en.wikipedia.org/wiki/SIMM/ [wikipedia.org]

  • Come on... Of all the news sites out there, people on this site should be better at using the proper capitalization. They're making 8 gigaBIT chips which will be seen in 128 gigaBYTE DIMMs

  • Faster and less power required. It's a win win. (probably lose a bit more at the cash register, though).

    • Less power required = Apple will take this occasion to use smaller batteries and make their computers*/phones/tablets thinner.

      Yes, even the iMac.

  • Classy use of Class (Score:5, Informative)

    by MiniMike ( 234881 ) on Tuesday April 05, 2016 @04:41PM (#51848889)

    FTFA:
    *10nm-class denotes a process technology node somewhere between 10 and 19 nanometers, while 20nm-class means a process technology node somewhere between 20 and 29 nanometers.

    This has the stink of a marketing department on it. Does anyone know what the actual size is? I'm guessing it's closer to 19 nm than to 10 nm. Still an impressive achievement if it meets their claims.

    Next year will their marketing department tout their 0 nm-class* process technology?

    • The story I read said that there were unconfirmed whispers that it was 18nm. It still IS impressive, like you said, but that 10nm-CLASS shit is so misleading. Just tell it like it is, it's already impressive enough.

      • Re: (Score:2)

        by Teun ( 17872 )
        Teenagers can be between 10 and nearly 20.

        • Re: (Score:1)

          by Anonymous Coward

          TEENagers are between thirTEEN and nineTEEN.

    • Re:Classy use of Class (Score:4, Informative)

      by tlhIngan ( 30335 ) <slashdot&worf,net> on Tuesday April 05, 2016 @05:59PM (#51849279)

      This has the stink of a marketing department on it. Does anyone know what the actual size is? I'm guessing it's closer to 19 nm than to 10 nm. Still an impressive achievement if it meets their claims.

      Well, general random logic is at 22nm, and memory class devices are usually a half-node ahead, so 16-18nm would be the size. Size is less important for general logic as most transistors will be larger than minimum size as transistors aren't the limiting factor - wiring is. Most transistors are larger because there's plenty of space as the wiring is keeping the transistor density low. Enough such that designers often put in extra transistors and gates in a design to be able to allow for metal layer redesigns without affecting transistor level placement.

      In memory units, minimum transistors are the storage elements, so the smaller they are, the more you can fit in. Plus, their extreme regularity means you want to minimize the cell size as much as possible.

      General logic is sparse enough that in what a few hundred thousand transistors occupies for random logic may be occupied by millions for memory blocks.

      • Well, general random logic is at 22nm, and memory class devices are usually a half-node ahead, so 16-18nm would be the size.

        CPUs [newegg.com] are at 14nm already.

    • It's even money for any process in production today whether there are *any* features that match the name of the node. "10nm" just means that it is the node that comes after "14nm".

      Any actual dimensions are closely held trade secrets that get scrubbed out of any material that makes it to the public, and most material circulated within the company. This is especially fun when you have to send a test case to an external CAD tool vendor where you have to scale it to some abstract units.

    • This is not marketing. Intel used to have a tick-tock modle shrinking the process down with a tick og tock every 18 month. Samsung chairman, as a response, said that Samsung does the same, only in 15 month. Now the poor engineers have to deliver this unachievable goal.

      They can not do this, and they find some feature in the design that is 10nm. and call it 10nm class.

      For comparison, the 65nm process has transistor gate length down to 25nm, pitch between lines over 120nm etc. So in reality, below 32nm there

  • row hammer resistance ? (Score:1)

    by Anonymous Coward

    Nice and all, but are these chips secured against row hammer style attacks ? (Or better said, are they reliable )
    The smaller the chip feature, the bigger of a problem this becomes.

  • Samsung say "10nm-class denotes a process technology node somewhere between 10 and 19 nanometers, while 20nm-class means a process technology node somewhere between 20 and 29 nanometers." They are carefully not saying exactly what scale technology is actually being used for this product and it could easily be 14nm or more.

  • Note the asterisk leading to Samsung's disclaimer: "10nm-class denotes a process technology node somewhere between 10 and 19 nanometers".
  • ... the market in 2016 or 2017. Do you remember the hype when articles claimed there soon would be no more need for classical DRAM because of that magic new technology of persistent memory?

    • Re: (Score:2)

      by Megol ( 3135005 )

      Actually no. 3D XPoint isn't (at least at the time) a replacement for DRAM as it is slower, it is a good replacement for (some) flash memory as it is persistent and have significantly better access times. Intel and Micron have never claimed otherwise.

  • And the rowhammer exploiters salivate.

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