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Data Storage

Toshiba, SanDisk Piloting 3D NAND That Doubles Previous Capacity 61

Lucas123 writes: Under a joint development agreement, Toshiba and SanDisk have begun pilot production of a new 48-layer 256Gb NAND flash chip in a brand new fab in Mie prefecture, Japan. The new X3 chips, which double capacity from 16GB to 32GB over the previous product, are made with triple-level cell (TLC) flash compared with Toshiba's last multi-level cell (MLC) chip, which stored two-bits per transistor. The chips are expected to begin shipping in products next year. The companies plan to use the new memory in a wide number of products, including consumer SSDs, smartphones, tablets, memory cards, and enterprise SSDs for data centers, the companies said.
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Toshiba, SanDisk Piloting 3D NAND That Doubles Previous Capacity

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  • by D.McG. ( 3986101 ) on Tuesday August 04, 2015 @09:38AM (#50248677)
    The data longevity of 3-bits per cell NAND is quite poor. MLC's 2-bits per cell still has me uneasy. Storing 1 of 8 voltage levels in an environment that leaks electrons over time is not for me. I'll wait for XPoint before upgrading my MLC SSD.
    • You know I thought you were wrong and that a Triple Level Cell had 3 levels per cell, storing about 1.6 bits. Apparently I was wrong. TLC despite standing for triple level cell apparently means in fact 8 levels per cell where as MLC (multi-level) is for 4 levels per cell.

      Whoever came up with these terms is nuts.

      • Makes perfect sense to me. Maybe its because I understand binary.
        • Makes perfect sense to me. Maybe its because I understand binary.

          How so? The cells have multiple voltage levels, they don't store binary. 3 levels is not the same as three bits.

          • 3 levels is not the same as three bits.

            You had posted that you just discovered that it is, and now you are posting that it isn't. Make up your mind.

            AC poster is right. You must have thought that SLC stored 0 bits since it had only 1 possible "level."

            • You had posted that you just discovered that it is, and now you are posting that it isn't.

              Try actually reading what I wrote before being overcome with smugness. MLC can measure multiple (i.e. > 2) voltage levels on the floating gate transistor. The number of bits is the log_2 of the number of distinct voltage levels.

              Calling something with 3 BITS that has 8 LEVELS triple level is silly. Why not just call it 3 bit cell. SLC sort of made sense from an EE point of view as being able to store one level as di

              • Calling something with 3 BITS that has 8 LEVELS triple level is silly.

                Especially since it only has 7 threshold levels... which was clearly explained to you hours before you made this reply. Typo, or dumbo?

                • Especially since it only has 7 threshold levels... which was clearly explained to you hours before you made this reply.

                  One threshold level = 2 distinguishable voltage levels. 7 thresholds = 8 distinguishable voltage levels. 3 bits is still not 3 levels by any normal definition of the word.

                  Typo, or dumbo?

                  It's entertaining that you're saying such things after making such elementary mistakes.

      • This pictures illustrates it clearly: http://www.pcper.com/files/ima... [pcper.com]
        And Wikipedia goes into more detail: https://en.wikipedia.org/wiki/... [wikipedia.org]

        SLC - Single Level Cell = 1 bit (2 states), most robust
        MLC - Multi Level Cell = (typically) 2 bits (4 states), ~1/10 of the lifespan of SLC
        TLC - Triple Level Cell = 3 bits (8 states), ~1/10 of the lifespan of MLC
    • by Kjella ( 173770 )

      Well, smaller process sizes also reduce write cycles. When they went from 2D to 3D they went back to a bigger process size with less defects due to all the layers. Though they had some controller/firmware issues the first 3D TLC NAND had more raw write cycles than state of the art planar MLC NAND. Of course now they're shrinking it again in the quest for even more storage, but the clock got a pretty good reset going from 1 layer to 48. Going from MLC to TLC is more of a variation that cuts write cycles to a

    • by fnj ( 64210 )

      The data longevity of 3-bits per cell NAND is quite poor. MLC's 2-bits per cell still has me uneasy. Storing 1 of 8 voltage levels in an environment that leaks electrons over time is not for me. I'll wait for XPoint before upgrading my MLC SSD.

      For pete's sake, MLC stands for multi-level cell, not four-state (two bit) cell. TLC is just a kind of MLC; it's not an either-or. TLC is eight-state (three bit). I realize we're kind of stuck with dumbed-down nomenclature, where MLC is used specifically for four-stat

    • by Bengie ( 1121981 )
      A research paper about Samsung VNAND had their TLC pegged between 5k and 60k write cycles, depending on how you tweaked the SSD for performance, but same density and less than a 3x difference in performance. VNAND is using a much larger processes while having greater densities. The larger process allows VNAND to have a lot more write cycles compared to regular TLC NAND. Of course the cycles will against get worse as the process shrinks, but VNAND inherently has more write cycles than NAND, even at the same
  • by Scottingham ( 2036128 ) on Tuesday August 04, 2015 @09:41AM (#50248703)

    Our storage mediums spun and made noises! And we liked it!

    • *cups ear* Whut?!

    • by Kjella ( 173770 )

      Back in my dad's day the memory spun and made noises [wikipedia.org]. No idea if he liked it.

      • Back in my dad's day the memory spun and made noises [wikipedia.org]. No idea if he liked it.

        Back in my day I was an operator on a Burroughs B3500. This machine had core memory. If you bumped the tape cart against the memory cabinet a little too hard it would cause a memory fault. Apparently those ferrite donuts didn't like being jostled.

    • by marciot ( 598356 )

      Our storage mediums spun and made noises! And we liked it!

      What is funny is that I recently upgraded my laptop to an SSD and I was flabbergasted that during disk access it made the exact same noise as it did when I had a regular hard disk. I thought I had been sold a fake SSD, but I’m getting approx 510MB/s on benchmarks, so I know it is legit. On further investigation the noise comes from where the speakers are located, so what I thought was hard disk noise was probably just electrical noise. My system makes the same soft buzzing sound on data access as it a

  • I wonder how these stack up... ahem with intels new offering. [dropboxusercontent.com]
  • Isn't Micron a step ahead with their 384Gb NAND chip?: http://www.micron.com/about/in... [micron.com]
    • Actually Samsung is ahead because they are the only ones selling 3D NAND right now. The Micron press release is more impressive than Toshiba's, sure, but it will take a couple of months before it gets into store shelves.

      • Yes. Samsung certainly did take the first steps into the 3D NAND world and is ahead in that regard. Still, Micron might be ahead in the labs and could leapfrog them if their "floating gate" approach is superior. It's too early for me to tell.
    • by robi5 ( 1261542 )

      Why is it that the video at the link you sent compares the revolution to the jump from a single-story office to a 32-story highrise, yet, as a result, memory is only 3x as much? I'd expect a multiple of 32, or even if the old stuff was TLC and the new is SLC, a multiple of almost 10.

      • Individual layers in 3D NAND are not as dense as planar NAND. The density should increase as the technology matures. I also suspect that they're intentionally holding back so that they can maximize profits with incremental improvements.

Think of it! With VLSI we can pack 100 ENIACs in 1 sq. cm.!

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