Processors and the Limits of Physics 168
An anonymous reader writes: As our CPU cores have packed more and more transistors into increasingly tiny spaces, we've run into problems with power, heat, and diminishing returns. Chip manufacturers have been working around these problems, but at some point, we're going to run into hard physical limits that we can't sidestep. Igor Markov from the University of Michigan has published a paper in Nature (abstract) laying out the limits we'll soon have to face. "Markov focuses on two issues he sees as the largest limits: energy and communication. The power consumption issue comes from the fact that the amount of energy used by existing circuit technology does not shrink in a way that's proportional to their shrinking physical dimensions. The primary result of this issue has been that lots of effort has been put into making sure that parts of the chip get shut down when they're not in use. But at the rate this is happening, the majority of a chip will have to be kept inactive at any given time, creating what Markov terms 'dark silicon.' Power use is proportional to the chip's operating voltage, and transistors simply cannot operate below a 200 milli-Volt level. ... The energy use issue is related to communication, in that most of the physical volume of a chip, and most of its energy consumption, is spent getting different areas to communicate with each other or with the rest of the computer. Here, we really are pushing physical limits. Even if signals in the chip were moving at the speed of light, a chip running above 5GHz wouldn't be able to transmit information from one side of the chip to the other."
Dupe (Score:5, Informative)
Same ArsTechnica article link and everything [slashdot.org]
There are no limits! (Score:1)
Well, except that every other technology has hit limits, except computers! They'll just endlessly get better. Forever.
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Yes, like Simon Newcomb [wikipedia.org] proved we had hit limits in heavier-than-air flight, in 1903!
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Your reasoning is false. Most AI algorithms are having a high level of parallelism which make them less susceptible to the single CPU physical limit. You can achieve incredible performance improvement on GPU and other parallel architectures.
The limit is human (Score:2)
Your reasoning is false. Most AI algorithms are having a high level of parallelism which make them less susceptible to the single CPU physical limit. You can achieve incredible performance improvement on GPU and other parallel architectures.
Good luck finding enough programmers that can write code with that level of parallelism.
Most of the multithreaded code I encounter in the real world simply slaps mutexes around things, whether or not they're needed, or even applied consistently. Most of the time, the mutex could be replaced with something cheaper, like atomic operations, or even unique state-transitions on a single volatile global variable.
Your experience may differ. Maybe I just have the back luck of working with morons most of the tim
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Good luck finding enough programmers that can write code with that level of parallelism.
Just buld an AI that programs AI in a highly parallel fashion. What could possibly go wrong?
This seems like a good time to meniton these (Score:5, Interesting)
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How are they energy efficient?
More gates == more static power draw.
Leaving a circuit switched on because you don't know when asynchronous transitions will arrive == more static power draw.
Global async design may have made sense in 1992, but not these days. Silicon has moved on.
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It depends.
Yes. In semiconductors, there's a basic tradeoff between static power dissipation and propagation latency. In a slow/low static current process, you might well be able to use asynchronous design to improve power efficiency. This is more the realm of RFID tags, payment cards and smart card chips. You won't be finding much of that going on in a desktop or phone CPU.
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I do understand it. That patent describes an asynchronous data transfer with rendezvous using a conventional quadrature handshake. I can't imagine that there isn't prior art. That is standard stuff. The date of the patent is 2006. I finished my degree in 1991 around the same time the amulet async ARM was beginning development. My tutor at college invented the async register file for the amulet.
The method it describes is slow because it requires a two round trips between source and destination. That is why c
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>Most power is drawn on transitions.
Most power is drawn in static leakage.
There, fixed that for you. It isn't 1990 any more, when what you said was true.
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I guess that's me then.
Every D-flip flop is an async circuit. We use a variety of other standard small async circuits we use that are a little bigger. Receiving clock-in-data signals like DS links is a common example. What you're talking about is async across larger regions.
Scaling fully asynchronous designs to a whole chip is a false economy. The area cost is substantially greater than a synchronous design and with the static power draw of circuits now dominating, the dynamic power savings of asynchronous
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Every D-flip flop is an async circuit. W.
How's that then? Would you care to explain, please, what you mean? .
My D-FFs here are totally synchronous: The D-input pops up at the output exactly with the rising clock edge + processing delay. And the latter is unavoidably indefinably.
A DFF is the basic element of a synchronous circuit, yes. But look inside a DFF and it's a basic async circuit with two (or 3 or 4) inputs and one (or two) outputs. That's why it requires you to maintain at least a minimum time gap between certain transitions on the inputs.
Don't they teach async design at college these days?
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You are conflating asynchronous circuits with asynchronous communication between mutually asynchronous circuits.
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http://www.embedded.com/design... [embedded.com]
http://www.technologyreview.co... [technologyreview.com]
http://www.scientificamerican.... [scientificamerican.com]
http://www.nytimes.com/2001/03... [nytimes.com]
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It's perfectly feasible in an async processor. You just have to hold the results in a buffer at the end of the computation until a timer fires. The timer being set to the longest the op might possibly take.
Async chips can have timers, they're just not driven by them.
Go vertical! (Score:5, Interesting)
Stacking dies or some other form of going from flat to vertical will get you around some of the signaling limits. If you look back at old supercomputer designs there were a lot of neat tricks played with the physical architecture to work around performance problems (for example, having a curved backplane lets you have a shorter bus but more space between boards for cooling). Heat is probably the major problem, but we still haven't gone to active cooling for chips yet (e.g. running cooling tubes through the processor rather than trying to take the heat off the top).
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Ah, Prime Radiant !
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But as you said yourself, CPUs (and GPUs) generate a lot more heat. They are already challenging enough on their own, imagine how hot the CPU or GPU at the middle of the stack would get with all that extra thermal resistance and heat added above and below it. As it is now, CPU manufacturers already have to inflate their die area just to fit all the micro-BGAs under the die and get the heat out.
Unless you find a way to teleport heat out from the middle and possibly bottom of the stack, stacking high-power ch
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There have been plenty of concept designs and current chips use 3d technology to an extent. The problem IS cooling. On a flat plane, you can simply put a piece of metal on top and it will cool it. Current chips sometimes stoke away close to 200W. With 3D designs, you need to build-in the heat transfer (taking up space you can't use for chips or communications) in between and both planes will produce equal amounts of heat so either heat transfer needs to be really, really good or you need a heat sink several
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Think different!
Maybe instead of stacking the chips, you put one on the bottom and have it double as a backplane and then mount additional dies to it vertically (like itty bitty expansion cards). Then you can get some airflow or other coolant flow in between those vertically mounted dies.
These kinds of funky solutions will only show up when they're cost-effective (that is, absolutely needed). The reason we stick with flat dies (and single die packages) is because it's cheaper to make/mount a single die in
Alpha Particles (Score:1)
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So how would we use alpha particles?
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So just why would alpha particles (which are basically a helium nucleus consisting of 4 really heavy particles) gonna be somehow faster than electrons (which are much lighter and take less energy to manipulate)?
Another problem is that we aren't currently using free-space electrons either, but electrons in a wave guide (where we lay down conductors to steer the electrons around the circuits we design). Not as easy to do with alpha particles...
can't cross chip in one clock. big deal. (Score:5, Interesting)
"Even if signals in the chip were moving at the speed of light, a chip running above 5GHz wouldn't be able to transmit information from one side of the chip to the other." ... in a single clock.
So in the 1980's I was a CPU designer working on what I call "walk-in, refrigerated, mainframes". It was mostly 100K-family ECL in those days and compatible ECL gate arrays. Guess what -- it took most of a clock to get to a neighboring card, and certainly took a whole clock to get to another cabinet. So in the future it will take more than one clock to get across a chip. I don't see how that is anything other than a job posting for new college graduates.
That one statement in the article reminds of when I first moved to Silicon Valley. Everybody out here was outrageously proud of themselves because they were solving problems that had been solved in mainframes 20 years earlier. As the saying goes: "All the old timers stole all our best ideas years ago."
Re:can't cross chip in one clock. big deal. (Score:5, Interesting)
Even AMD's Athon designs did that. Intels latest offerings can be coerced into executing 5 operations per cycle that are each 3 cycle latency, and then thats on a single core with no SIMD.
Its not how quickly the CPU can produce a value.. its how frequently the CPU can retire(*) instructions.
(*) Thats actually a technical term.
Re:can't cross chip in one clock. big deal. (Score:4)
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> The fact that a simple integer addition operation has a latency of 2 or 3 clock cycles doesnt prevent the CPU from executing 3 or more of those additions per clock cycle.
That's just wrong. It does't take three clock periods to propagate through an adder on today's silicon unless it's a particularly huge adder. It might take several cycles for an add instruction to propagate though a CPU pipeline, but that is completely different.
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Maybe he was talking FADD.
In a float addition, you need to denormalize the inputs, do the actual addition and then normalize the output. Three well-defined pipelining steps, each embodying one distinct step of the process.
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No, he wasn't. From his post: "simple integer addition"
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Are you saying electrons were moving slower in the 80's?
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There is no such constant in physics like the speed of the electron. The speed of the electron depends on the medium it is travelling into as well as the force applied to it. That's why the electron's speed is not the same in an old CRT monitor than in the LEP (Large Electron-Positron Collider, the ancestor of the LHC in Geneva).
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Erm, well true, but same goes for light, yet we speak about the speed of light as a constant...
The point I was trying to make, obviously, Slashdot of old has gone away, so I guess you need to pencil it out in stone, was that the guy is claiming a clock cycle took ages to propagate through the systems, which tells us he has no idea, what was and is going on in a computer. Now syncing a clock across several huge monolithic machines back then was easy, because a clock cycle was happening almost at a walking pa
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That's because we talk about the speed of light - in a vacuum - which is a constant....
...absent large gravitational fields.
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The speeds of the electrons is immaterial. The speeds of the electric field in the wires is what matters.
The electrons move really slowly.
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The speeds of the electrons is immaterial.
Outside of the transistor channels, that is. :-)
Re:can't cross chip in one clock. big deal. (Score:4, Informative)
Well, clearly moving mainframe people to OS/2 development wouldn't have been a so great idea. The mainframe segment was much more profitable than the PC segment where the profit margin are so thin IBM decided to sell the whole division to Lenovo. The money is elsewhere.
And do not forget memory management has to be reinvented because there was IP rights on the MVS algorithms IBM wasn't willing to transfer to OS/2. In these old times, the PC market and mid-range market were perceived as a threat by the big mainframe guys at IBM which were still the guys at the top in the hierachy. The technical side is just the lesser part of this problem.
Reminds me of Lord Kelvin... (Score:1)
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Well, Peter might be a good liberal leftie, everything is relative in that mindset.
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As Einstein showed, yes things are relative.
"Things," eh? Any particular "things"?
He also showed that one particular thing was absolute, if you recall.
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Nope. Einstein showed consequences of the speed of light being a constant of nature. He didn't show or even predict that it was one, that was done by Maxwell's equations and various attempts to measure Earth's velocity relative to luminous aether (which turned out to be "zero").
And as it happens, one of those consequences is that timewise and spacewise distance are relative.
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It is very plain that many parts of the Bible are not meant to be taken literally. The age of the earth being the most obvious.
what diminishing returns? (Score:2)
Each semiconductor node shrink is faster and more power effiecient than the previous. For instance, TSMC 20nm process is 30% higher speed, or 25% less power than 28nm. Likewise, 16nm will provide 60% power saving than 20nm.
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Something called leakage grows as process size goes down.
For 40nm, leakage was around 1 to 4% depending on the process variant chosen.
For 28nm, is jumped to 5 to 10%.
For 20nm, it is around 20 to 25%. This means that just turning a circuit on and doing nothing (0 Mhz) adds to the power consumption.
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If you have a crappy old planar process maybe.
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Not really, because the tech is improving all the time. At 20nm the have high-k metal gates and at 16nm FinFETs.
So what (Score:1)
You don't need to constantly shrink everything. My computer is about 2 feet tall and wide. I don't care if it's a couple more inches in any direction. Make a giant processor that weighs 20 pounds.
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shrinking can allow for higher speed.
that's what makes this article sound dumb just by the blurb(..that it takes x amount of time to get to the other side of the chip and thus the chip can't run faster bullcrap).
I mean, current overclocking records are way, way, wayyy over 5ghz. so what is the point?
Re:So what (Score:4, Informative)
Nobody says 5GHz is impossible. Read it.
It says that you can't traverse the entire chip while running at 5GHz. Most operations don't - why? Because the chips are small and any one set of instructions tends to operate in a certain smaller-again area.
What they are saying is that chips will no longer be synchronous - if chips get any bigger, your clock signal takes too long to traverse the entire length of the signal and you end up with different parts of the chips needing different clocks.
It's all linked. The size of the chip can get bigger and still pack in the same density, but then the signals get more out of sync, the voltages have to be higher, the traces have to be straighter, the routing becomes more complicated, and the heat will become higher. Oh, and you'll have to have parts of it "go dark" to avoid overheating neighbours, etc. This is exactly what the guy is saying.
At some point, there's a limit at which it's cheaper and easier to just have a bucket load of synchronous-clock chips tied together loosely than one mega-processor trying to keep everything ticking nicely.
And current overclocking records are only around 8GHz. Nobody says you can't make a processor operating at 10THz if you want. The problem is that it has to be TINY and not do very much. Frequency, remember, is high in anything dealing with radio - your wireless router can do some things at 5GHz and, somewhere inside it, is an oscillator doing just that. But not the SAME kinds of things as we expect modern processors to do.
Taking account that most of those overclocking benchmarks probably operate in small areas of the silicon, are run in mineral oil or similar and are the literal speed of a benchmark over a complicated chip that ALREADY takes account that signals take so long that clocks can get out of sync across the chip, we don't have much leeway at all. We hit a huge wall at 2-3GHz and that's where people are tending to stay despite it being - what, a decade or more? - since the first 3GHz Intel chip. We add more processors and more core and more threading but pretty much we haven't got "faster" over the last decade, we're just able to have more processors at that speed.
No doubt we can push it further, but not forever, and not with the kind of on-chip capabilities you expect now.
With current technology (i.e. no quantum leaps of science making their way into our processors), I doubt you'll ever see a commercially available 10GHz chip that'll run Windows. Super-parallel machines running at a fraction of that but performing more gigaflops per second - yeah - but basic core sustainable frequency? No.
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My words fail me. The operation is clocked. That the clock doesn't happen at the same time everywhere doesn't change the nature of the operation being clocked. And
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Lightspeed (Score:2)
Yet another reason to find a way around the speed of light.
Actually I've always said (jokingly) that if anyone does find a way to go FTL, it'll be the computer chip manufacturers. In fact Brad Torgersen and I had a story to that effect in Analog magazine a couple of years ago, "Strobe Effect".
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Mastering and ultimately harnessing quantum entanglement as it pertains to quantum computing and the limits we face right now go right out the window.
Density limit - not computational limit (Score:3)
Congratulations, you identified the densest possible circuits we can make. That doesn't even give an upper bound to Moore's Law, let alone an upper bound to performance.
Moore's Law is "the number of transistors in a dense integrated circuit doubles every two years". You can accomplish that by halving the size of the transistors, or by doubling the size of the chip. Some element of the latter is already happening - AMD and Nvidia put out a second generation of chips on the 28nm node, with greatly increased die sizes but similar pricing. The reliability and cost of the process node had improved enough that they could get a 50% improvement over the last gen at a similar price point, despite using essentially the same transistor size.
You could also see more fundamental shifts in technology. RSFQ seems like a very promising avenue. We've seen this sort of thing with the hard drive -> SSD transition for I/O bound problems. If memory-bound problems start becoming a priority (and transistors get cheap enough), we might see a shift back from DRAM to SRAM for main memory.
So yeah, the common restatement of Moore's Law as "computer performance per dollar will double every two years" will probably keep running for a while after we hit the physical bounds on transistor size.
Re:Density limit - not computational limit (Score:4, Informative)
Moore's Law is "the number of transistors in a dense integrated circuit doubles every two years". You can accomplish that by halving the size of the transistors, or by doubling the size of the chip. Some element of the latter is already happening - AMD and Nvidia put out a second generation of chips on the 28nm node, with greatly increased die sizes but similar pricing. The reliability and cost of the process node had improved enough that they could get a 50% improvement over the last gen at a similar price point, despite using essentially the same transistor size.
Bad example, the initial yield on 28nm was so bad that the initial pricing was hugely impacted by wafer shortages. Many fabless customers reverted to the 40nm node to wait it out. TSMC eventually got things sorted out so now 28nm has reasonable yields.
Right now, the next node is looking even worse. TSMC isn't counting on the yield-times-cost of their next gen process to *ever* get to the point when it crosses over 28nm pricing per transistor (for typical designs). Given that reality, it will likely only make sense to go to the newer processes if you need its lower-power features, but you will pay a premium for that. The days of free transistors with a new node appear to be numbered until they make some radical manufacturing breakthroughs to improve the economics (which they might eventually do, but it currently isn't on anyone's roadmap down to 10nm). Silicon architects need to now get smarter, as they likely won't have many more transistors to work with at a given product price point.
If memory-bound problems start becoming a priority (and transistors get cheap enough), we might see a shift back from DRAM to SRAM for main memory.
Given the above situation, and that fast SRAMs tend to be quite a bit larger than fast DRAMs (6T vs 1T+C) and the basic fact that the limitation is currently the interface to the memory device, not the memory technology, a shift back to SRAM seems mighty unlikely.
The next "big-thing" in the memory front is probably WIDEIO2 (the original wideio1 didn't get many adopters). Instead of connecting an SoC (all processors are basically SoC's these days) to a DRAM chip, you put the DRAM and SoC in the same package (either stacked with through silicon vias or side-by-side in a multi-chip package). Since the interface doesn't need to go on the board, you can have many more wire to connect the two, and each wire will have lower capacitance which will increase the available bandwidth to the memory device.
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Odd that TSMC is so pessimistic, because Intel claims their 22nm node was their most high-yield ever, and even their 14nm yield is pretty high for this early in development. Perhaps the multi-gate FinFETs helped? I know TSMC is planning FinFET for 16nm later this year. That's not a "radical manufacturing breakthrough" but it is a pretty substantial change that could change their yields considerably.
Unconventional architectures and quantum computing (Score:2)
I see increasing emphasis in the future on unconventional architectures to solve certain problems
http://www.research.ibm.com/ar... [ibm.com]
http://en.wikipedia.org/wiki/Q... [wikipedia.org]
and a little further into the future, single molecule switches and gates.
http://en.wikipedia.org/wiki/M... [wikipedia.org]
We have a ways to go, but at some point we are going to have to say bye-bye to the conventional transistor.
What we need for efficiency (Score:2)
Power use is NOT proportional with voltage (Score:1)
Maybe Markov should go back to school.. Power use is modeled as voltage squared, not as proportional.
Apologies to Markov if it is just the summary that is wrong.
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That's true for active power. (V^2/R). For leakage power, it's even worse. That looks closer to exponential. [eetimes.com] I've seen chip for which leakage accounted for close to half the power budget.
Supposedly FinFET /Tri-gate will help dramatically with leakage. We'll see.
Is that really correct?? (Score:1)
Power use is proportional to the chip's operating voltage, and transistors simply cannot operate below a 200 milli-Volt level
Wow. To me it is like P~U^2. So proportional, but not linear.
And where would that 200 mV level come from? In my understanding it depends very much on the semiconductor used.
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200mV likely comes from a generic analysis of CMOS on Silicon wafer oxide assuming you don't want a leakage factor more than 50% the current (most of which comes from the subthreshold conduction current) and you don't do any weird body-biasing techniques (which would consume lots of circuit area). It isn't a hard number but a general ballpark. Since everyone is scaling down the supply voltage, we must also scale down the threshold voltage and then the amount a signal is below the threshold voltage when you
Seems simple enough (Score:2)
You need single isotope silicon. Silicon-28 seems best. That will reduce the number of defects, thus increasing the chip size you can use, thus eliminating chip-to-chip communication, which is always a bugbear. That gives you effective performance increase.
You need better interconnects. Copper is way down on the list of conducting metals for conductivity. Gold and silver are definitely to be preferred. The quantities are insignificant, so price isn't an issue. Gold is already used to connect the chip to out
Can you fit that in a laptop? (Score:2)
Heat is only a problem for those still running computers above zero Celsius.
Good luck fitting your frozen computer into a laptop case or something else that can be used while riding public transit. Not everybody is content to just "consume" on a "mobile device" while away from mains power.
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Hemp turns out to make a superb battery. Far better than graphene and Li-Ion. I see no problem with developing batteries capable of supporting sub-zero computing needs.
Besides, why shouldn't public transport support mains? There's plenty of space outside for solar panels, plenty of interior room to tap off power from the engine. It's very... antiquarian... to assume something the size of a bus or train couldn't handle 240V at 13 amps (the levels required in civilized countries).
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Please explain how your vision is different from, say, OpenCL?
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OpenCL is highly specific in application. Likewise, RDMA and Ethernet Offloading are highly specific for networking, SCSI is highly specific for disks, and so on.
But it's all utterly absurd. As soon as you stop thinking in terms of hierarchies and start thinking in terms of heterogeneous networks of specialized nodes, you soon realize that each node probably wants a highly specialized environment tailored to what it does best, but that for the rest, it's just message passing. You don't need masters, you don
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Well, since the CPU already specializes in general-purpose serial computation, other nodes in a heterogenous environment must logically specialize for either generic parallel computation or specific applications, otherwise you have just plain old SMP.
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Let's start with basics. Message-passing is not master-slave because it can be instigated in any direction. If you look at PIC Express 2.1, you see a very clear design - nodes at the top are masters, nodes at the bottom are slaves, masters cannot talk to masters, slaves cannot talk with slaves, only devices with bus master support can be masters. Very simple, totally useless.
Ok, what specifically do I mean by message passing? I mean, very specifically, a non-blocking, asynchronous routable protocol that con
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This sounds a lot like NUMA. Which, I might add, absolutely requires differentiating between local and non-local memory, since the latter is much slower.
Like GPUs have done since the time of AGP? Or did you mean memory wil
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Single isotope silicon? Silicon wafers surfaces (where the transistors are) are generally doped with ions using diffusion and etched, and the most serious defects are usually parametric due to patterning issues. We've go a long ways to go before actually isotope purity is going to be a limiting factor...
Conductivity of gold vs copper? Copper is a better conductor than gold (although silver is a better conductor than both of them). The reason that gold is used for *connections* is that it is more malle
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Alas, my knowledge of this is becoming obsolete, so I could easily be wrong.
popular science is back (Score:1)
one day, computers will be twice as fast and ten times as big -- vacuum tubes? meet transistors.
computers can't get any more popular because we'll run out of copper. . . zinc. . . nickel -- welcome to silicon. Is there enough sand for you?
everything will stay the way it is now forever. things will never get any faster because these issues that aren't problems today will eventually become completely insurmountable.
relax. take it easy. we don't solve problems in-advance. capitalism is about quickly solvi
Wrong, wrong, wrong (Score:3)
Wrong.
Wrong. Get the voltage too low and they won't be fast, but they won't necessarily stop working.
And of course, the analysis of the communications issue is also wrong.
There are obvious and non-obvious physical limitations that limit scaling, but nobody is being helped by this muddy, error-ridden presentation.
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Didn't you get the memo [slashdot.org]? Hemp seeds are better than graphene. Plus you can get high while growing the seeds.
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President Romney agrees with you too.
I see you are from the reality where the Republican Senate repealed the laws of physics. The time-space continuum is altering already.
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Right, which is why we live in the leisure society with 10 hour workweeks, everyone has a flying car, a Star Trek replicator and personal warp drive space ships.
You are clueless. You live in a bubble of technology created by people infinitely smarter than you and you are happy with comic-book levels of understanding.
The marching morons! (Score:2)
You are clueless. You live in a bubble of technology created by people infinitely smarter than you and you are happy with comic-book levels of understanding.
So you're saying that Cyril M. Kornbluth [wikipedia.org] was right? Race you to Venus!
Re: Lightfoot (Score:4, Informative)
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Right. There's no way you'd run a signal across a one inch chip and expect to get anything useful out the other end.
In days of yore, the signal would be buffered a few times.
These days it would pass through 5 clock domains and power boundaries and so have to be rebuffered, resynchronized, levelshifted and firewalled at each stage. But this is normal and we do it all the time.
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I don't think you design chips do you?
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The speed of light in a vacuum is about 3.0 x 10^8 m/sec, not 0.3 x 10^8 m/sec. Still, your 6" per nanosec at half the speed of light in a vacuum is about right.
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Please see propagation delay [wikipedia.org].
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There is also the assumption that the chip structure is 2-D. This is already not totally true, though there are tremendous heat problems as you start stacking layers. This is one of the attractions of "spintronics"...state can be switched with less heat.
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https://www.youtube.com/watch?v=1-vcErOPofQ [youtube.com]
It's a 10 minute Letterman interview but well worth the time...
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remember 512k is good enough for everyone.
we aren't quite there yet...
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And you think printf() and strtol() are major bottlenecks worth dedicated silicon area why?
Modern CPUs already have many accelerators for high end functions, such as numerical computations, cryptography, and the all important memcpy. (Memory copies are a traditional bottleneck, and general enough that they can be easily offloaded.) They come in two forms—specialized SIMD/vector instruction sets, and dedicated blocks for high-level functions that take multiple microseconds. An example of the former a
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Pipelining increases performance and instructions per cycle, but at the cost of power efficiency as branches cause a pipeline flush.
The problem is balancing area, performance, and performance.
There are obviously limits the the ability to make smaller circuits, even the ones described as 14nm are not really 14 in the same way 160 was 160. There is a lot of wasted space because of the LELE process and the need to minimise crosstalk and distortion.
The real limit however is not how much better X-ray exposure wi