SRI/Cambridge Opens CHERI Secure Processor Design 59
An anonymous reader writes with some exciting news from the world of processor design: Robert Watson at Cambridge (author of Capsicum) has written a blog post on SRI/Cambridge's recent open sourcing of the hardware and software for the DARPA-sponsored CHERI processor — including laser cutting directions for an FPGA-based tablet! Described in their paper The CHERI Capability Model: Reducing Risk in an age of RISC, CHERI is a 64-bit RISC processor able to boot and run FreeBSD and open-source applications, but has a Clang/LLVM-managed fine-grained, capability-based memory protection model within each UNIX process. Drawing on ideas from Capsicum, they also support fine-grained in-process sandboxing using capabilities. The conference talk was presented on a CHERI tablet running CheriBSD, with a video of the talk by student Jonathan Woodruff (slides).
Although based on the 64-bit MIPS ISA, the authors suggest that it would also be usable with other RISC ISAs such as RISC-V and ARMv8. The paper compares the approach with several other research approaches and Intel's forthcoming Memory Protection eXtensions (MPX) with favorable performance and stronger protection properties. The processor "source code" (written in Bluespec Verilog) is available under a variant of the Apache license (modified for application to hardware). Update: 07/16 20:53 GMT by U L : If you have any questions about the project, regular Slashdot contributor TheRaven64 is one of the authors of the paper, and is answering questions.
Although based on the 64-bit MIPS ISA, the authors suggest that it would also be usable with other RISC ISAs such as RISC-V and ARMv8. The paper compares the approach with several other research approaches and Intel's forthcoming Memory Protection eXtensions (MPX) with favorable performance and stronger protection properties. The processor "source code" (written in Bluespec Verilog) is available under a variant of the Apache license (modified for application to hardware). Update: 07/16 20:53 GMT by U L : If you have any questions about the project, regular Slashdot contributor TheRaven64 is one of the authors of the paper, and is answering questions.
To make things more secure, make them simpler (Score:1)
Complexity is bad for security.
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Capabilities are simpler than "simple" paged memory management. Every pointer carries permissions, enforced in hardware, instead of requiring several layers of software to perform their own ownership management.
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To paraphrase Einstein, "security should be as simple as possible, but no simpler."
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Simplicity is an illusion we place on reality. In reality, simplicity is merely trading complexity for a predefined set of rules that only come about through even more complex ideas.
This is exactly what they are doing. They are trading the complexity of 5 million different programmers trying to be secure for hardware designed by a few really smart people.
In this case, things become simpler for everyone, including the hackers, as they only have to hack one model. However, since the compilers are in on it, th
Re:To make things more secure, make them simpler (Score:4, Insightful)
Laser cutting directions! (Score:5, Insightful)
Breathless excitement!
The achievements in the rest of this paper far outweigh the existence of a tablet built on this foundation.
They've created their own 64-bit processor! They've implemented a compiler for it! They've ported FreeBSD to it! That's some seriously impressive stuff!
But the leader has to be the laser cut tablet assembly. :-(
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Hogging out a hole : to reverse-3D print
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Re:Laser cutting directions! (Score:4, Informative)
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Impressive is also the dare to implement a capability based model with some backing that could lead to consumer products eventually. How many decades this has been put to side now in the general market?
Most of the early capability systems (with the exception of the M-Machine from MIT) were extreme-CISC chips. They implemented complex capability walking so you could have multiple levels of indirection before you got to the . We aim to provide enough hardware support that you can implement these things in software, in a way that can't be bypassed. We're also aiming for a single hardware abstraction that scales from per-object bounds checking up to large sandboxes (think NaCl, but cheap and hardware-enfor
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Most of the early capability systems (with the exception of the M-Machine from MIT) were extreme-CISC chips.
Or CISC and extreme-CISC multi-chip processors, such as the Cambridge CAP computer [wikipedia.org], the Plessey System 250 [wikipedia.org], the Flex machine [wikipedia.org], and the IBM System/38 [wikipedia.org].
4chan comment (Score:2, Offtopic)
>CHERI processor
Really? Cheri?
http://cheri.com/ [cheri.com] You have been promoted!
NOT SAFE FOR WORK.
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BMO
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I know it's poor form to bitch about moderation, but "offtopic?" Really?
It never crossed anyone's mind to type the name into a web browser? You know, just to make sure that it didn't link to something like lemonparty?
--
BMO
Any questions? (Score:5, Informative)
source code of the processor? But software patents (Score:2)
A processor is a piece of hardware, correct?
TFS says the Verilog source code of the processor is available. "Source code" sounds like software. I bet you can even run that source code on a general purpose CPU, can't you?
So is the processor hardware, software, or are the people who scream about "software patents" utterly clueless about computer engineering?
Re:source code of the processor? But software pate (Score:5, Informative)
In theory, you could also take the verilog and generate a custom chip. In practice, you wouldn't want to without some tweaking. For example, our TLB design is based on the assumption that TCAMs are very expensive but RAM is very cheap. This is true in an FPGA, but is completely untrue if you were fabbing a custom chip.
Although we use the term 'source code', it's perhaps better to think of it as the code for a program that produces a design of a processor, rather than the source code for a processor.
In terms of software patents, there's some annoying precedent that a software implementation of a architectural patent can be infringing. The MIPS architecture that we implement has LWR and LWL instructions that accelerate unaligned loads and stores. These were patented (the patents have now expired) and the owners of the patent won against someone who created a MIPS implementation where these two instructions caused illegal instruction traps and were emulated in software. The software implementations were found to infringe the hardware patent.
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The 'source code' we are talking about is not running on a processor. ;)
It is written in a HDL, a 'hardware description language'. The compiler is generating a chip layout which is then burned into an FPGA, a 'field programmable gate array' (or was it 'free'?)
So they use a 'programming language' to describe the logic, the circuits, of the processor.
The final result ofc is hardware that is capable of running FreeBSD and user land applications.
Hope that helped
Re:How does it compare to Unisys MCP ? (Score:5, Informative)
There's a little bit of comparison to the Burroughs architecture that was one of the forerunners of the Unisys architecture in the paper. I'm not overfly familiar with the later Unisys MCP, so this may be wrong:
Our approach was explicitly intended to work with language that are not memory safe (i.e. C and friends). If you have a memory-safe language, then there is some cost associated with enforcing the memory safety in software, which CHERI can assist with, but you don't see much of a win.
As soon as you start mixing languages, you get the worst of all worlds. A typical Android application is written in C and Java (and some other things) and so gets all of the memory safety of C, plus all of the performance of Java. A single pointer error in the C code can corrupt the Java heap. One of my students last year implemented a modified JNI on CHERI that allows this sort of mixing but without the disadvantages. Java references are passed to C code as sealed capabilities, so the C code can pass them back to the JVM, but can't dereference them. The C code itself runs in a sandbox (C0 - the capability register that identifies the region of memory that normal MIPS loads and stores can use - is restricted to a smallish subset of the total [virtual] address space) so any pointer errors inside the C are constrained to only touch the C heap (of that particular sandbox - there can be a lot). He demonstrated running buggy and known-exploitable code in the JNI, without it compromising the Java code, with a very small overhead for calling in and out of the sandbox. Most interestingly, he was also able to enforce the Java security model for native code: the sandboxed code couldn't make system calls directly and had to call back into the currently active Java security monitor to determine whether it was allowed to.
Another of my students implemented an accurate (copying, generational) garbage collector for capabilities. This can be used with C code, as long as the allocator is outside of the normal C0-defined address space (otherwise pointers can leak as integers into other variables and be reconstructed). In particular, you can use this to track references to high-level language objects as they flow around C code and either invalidate them or treat them as GC roots, so you don't get dangling pointer errors. Or you can just use his allocator in C and have fully GC'd C code...
My understanding of MCP is that it uses high-level languages in the kernel, but does nothing to protect (for example) typesafe ALGOL code from buggy C code within the same userspace process.
Re:How does it compare to Unisys MCP ? (Score:5, Informative)
Currently, Ohloh.net is aware of around 11 billion lines of C/C++ code. I'm including C++ because, while it's possible to write memory-safe C++, all of the evil pointer tricks that are permitted in C are also allowed in C++. Rewriting 11 billion lines of code, even in a language that is 100 times more expressive than C, would be a daunting task. Note that Ohloh only tracks open source code in public repositories: there's a lot more that's in private codebases.
For a fully memory-safe language, you need things like bounds checks on array accesses. Some research from IBM about 10 years ago showed that, with JVMs of the time, the cost of bounds checks accounted for the vast majority of the difference in performance between C++ and Java implementations of the same algorithms. They did some nice work on abstractions that allowed most bounds checks to be statically elided, but their approach never made it into the language. The overhead is somewhat hidden by superscalar architectures (the bounds check is done in parallel and the branch is predicted not-taken), but not on low-power in-order chips like the Cortex A7 that you'll find in a lot of modern mobile phones.
Re:How does it compare to Unisys MCP ? (Score:5, Informative)
I appreciate your comments, but would like to add that it appears to me that correctness+security has by now become more important for applied computer science than processing throughput.
Yes, that's one of the motivations for our work. Now seems to be the time when it's possible to persuade CPU vendors that dedicating a little bit more hardware to security is valuable. It isn't quite the dichotomy that you describe though, because you can either implement security features in software or hardware and doing so in hardware can mean that you see a performance improvement for the sorts of use cases that people increasingly care about.
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Coming late to this party, I can only share this one datapoint: If I recollect right, it was the hardware on the Burroughs Large Systems that was memory-safe. Arrays were done as Segment Descriptors, and if you indexed outside the segment it raised an exception. Byte-addressed (for 6-bit, 8-bit, etc bytes) were done as "String Descriptors" that referred to the Segment Descriptor.
The only other hardware I know of that did this lately was the UCSB P-system; there may be others since then.
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Yup. Compiling for the Burroughs architecture was easier than many segment-based systems, because they allowed segment descriptors to be placed in main memory, with the CPU responsible for tracking the value type by updating a tag. We adapt this slightly so that we only require one tag bit per 256 bits of main memory (the paper describes the implementation of this in some detail, but I'm happy to answer questions) to be able to safely store capabilities in main memory. Our design also allows normal C dat
Re:Any questions? (Score:5, Informative)
Look this gifthorse in the mouth (Score:1)
Are there independent third-party audits underway? If DARPA likes it, I'm suspicious.
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The flippant answer is all that your paranoia deserves. The work was undertaken by SRI and The University of Cambridge. The funding was provided by DARPA, but that's the extent of their involvement (other than creating a program with the goal of being able to redesign any aspect of computing with security in mind).
The code is no more or less meriting an independent audit than any other open source code. Less, actually, because we don't anticipate anyone actually using our open source reference impleme
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The flippant answer is all that your paranoia deserves.
A healthy amount of paranoia is a must in the security industry. Every piece of security hardware or sofware demands third-party evaluation, even that made by people you trust completely. Not all flaws are deliberate. Thank you for your time, and (at last) thoughtful response.
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This is an interesting design. Have you thought about maybe posting seL4 to it once that's open-sourced in a couple of weeks? /akr
Yes, we're looking forward to the seL4 release. Somewhat cautiously, as there's no mention of a license (if it's GPL'd, we probably won't put any effort into it). In CHERI, we have store-capability and load-capability permissions on both capabilities and pages. To implement the seL4 model (where capabilities are stored in special pages), we'd only need to use the TLB-grandularity protections, but it would be more interesting to provide fine-grained capability storage, which would reduce a bit of the diff
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We haven't specifically looked at key storage, but we are looking at potential ways of extending the approach to heterogeneous multicore systems, so that access to main memory could be delegated to accelerators (at varying levels of coupling) via capabilities and capabilities could be used to mediate access to accelerators. In this scheme, it would be possible to provide an encryption coprocessor that would store keys internally and perform encryption and decryption operations on blocks of memory delegated
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Is the code for the LLVM support publically available / do you have a link for it?
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Yup, it's on GitHub in two repositories, one for LLVM [github.com] and one for clang [github.com]. We've been pushing the fixes for MIPS IV upstream, but there are some changes to the mid-level optimisers to make them aware that not all pointers are integers and some extensions to the platform-independent code generators for the same.
We've upstreamed all of the FreeBSD changes required for the base processor (BERI) and the development boards, so FreeBSD 10 will run out of the box on CHERI (it just won't expose any of the capabil
Acronyms with multiple meanings (Score:1)
Multi-Pointer X, also called MPX