Intel To Offer Custom Xeons With Embedded FPGAs For the Data Center 80
MojoKid (1002251) writes For years, we've heard rumors that Intel was building custom chips for Google or Facebook, but these deals have always been assumed to work with standard hardware. Intel might offer a different product SKU with non-standard core counts, or a specific TDP target, or a particular amount of cache — but at the end of the day, these were standard Xeon processors. Today, it looks like that's changing for the first time — Intel is going to start embedding custom FPGAs into its own CPU silicon. The new FPGA-equipped Xeons will occupy precisely the same socket and platform as the standard, non-FPGA Xeons. Nothing will change on the customer front (BIOS updates may be required), but the chips should be drop-in compatible. The company has not stated who provided its integrated FPGA design, but Altera is a safe bet. The two companies have worked together on multiple designs and Altera (which builds FPGAs) is using Intel for its manufacturing. This move should allow Intel to market highly specialized performance hardware to customers willing to pay for it. By using FPGAs to accelerate certain specific types of workloads, Intel Xeon customers can reap higher performance for critical functions without translating the majority of their code to OpenCL or bothering to update it for GPGPU.
To help prevent people from buying AMD and nVidia (Score:4, Insightful)
Intel Xeon customers can reap higher performance for critical functions without translating the majority of their code to OpenCL or bothering to update it for GPGPU
In other words, to help prevent people from buying AMD and nVidia products.
Re:To help prevent people from buying AMD and nVid (Score:5, Interesting)
No ignore that entire last sentence, it's dumb. FPGAs don't do floating point very well for one and even their integer performance will never rival a GPGU either in performance, or power. For another, I can and do, use both FPGAs and OpenCL/GLSL in my daily life and would infinitely prefer to port my functions to OpenCL over an FPGA. It's quite a bit more work to synthesize and validate an FPGA design than it is to write OpenCL code and debug the usual way.
I think it's far more likely customers are implementing custom hardware solutions using the FPGA related to power management, server management and datastructure infrastructure that can only be done with an FPGA in certain power domains. I say this having designed servers and dealt with the feature requests.
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s/datastructure/datacenter/
caffeine, it's what should have been for breakfast.
Re:To help prevent people from buying AMD and nVid (Score:5, Informative)
FPGAs don't do floating point very well for one and even their integer performance will never rival a GPGU either in performance, or power.
Sure, and a hammer makes a terrible screwdriver. GPUs are specifically designed for register-to-register SIMD operations, so of course they are going to excel at that. But an FPGA is going to be better at bitstream operations, including many hashing and encryption algorithms.
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Re: To help prevent people from buying AMD and nVi (Score:1)
Dude, Altera FPGAs already do OpenCL (says me, a guy who helped implement it).
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That's great, so they're going to port their code to Open CL, then run it on your FPGA? Why not just buy a GPU and plug it in?
If they're really set on your FPGA, why not buy a PCIe attached version of your FPGA? Xilinx has them and they go up to pcie v3 x8? What about power? Datacenters care, FPGAs are going to use more power. Why is this a good idea?
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Some workloads perform much better on an FPGA, notably, realtime encoding/compression of HD H.264 video. I know because I've worked on such a broadcast quality encoder [currently being used by some major distribution outlets]. While you're right that it's harder to program an FPGA [in particular, validate the design], the performance gains can be huge. In particular, calculating motion vectors gets a win.
Note that H.264 DCT's are integer ones. And, with Intel's hybrid/onchip implementation, the FPGA log
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So, does the FGPA "code" get swapped on a context switch?
Code (Score:1)
"By using FPGAs to accelerate certain specific types of workloads, Intel Xeon customers can reap higher performance for critical functions without translating the majority of their code to OpenCL or bothering to update it for GPGPU"
LOL. But they will have to translate it to Verilog or VHDL, which is far harder.
Re:Code (Score:4, Interesting)
Less of a "Hey, let's do this instead of GPU compute!" and more of a "It sucks that our weirdo application-specific operation is probably never going to be one of Intel or AMD's extensions to x86; but this is the closest we can get to having it added" thing.
Re:Code (Score:4, Informative)
My guess would be that the real perk is bandwidth and latency. Unless Intel really phones it in on integration, the FPGA should have about the fastest, lowest-latency, link to the CPU, possibly even some of the cache, especially if they throw in a big chunk of eDRAM, as they have for 'Iris Pro' parts, that money can buy.
As usual, the slashdot post has the absolute worst story link. compare http://www.enterprisetech.com/... [enterprisetech.com] which gives you links to where it gets its info, namely https://communities.intel.com/... [intel.com] and http://gigaom.com/2014/06/18/i... [gigaom.com] ... the latter is the interesting link because it tells us that the FPGA will have access to main memory. I personally would presume that means it's tied into the memory controller somehow.
Less of a "Hey, let's do this instead of GPU compute!" and more of a "It sucks that our weirdo application-specific operation is probably never going to be one of Intel or AMD's extensions to x86; but this is the closest we can get to having it added" thing.
What I began fantasizing about immediately upon reading the article was some sort of optimizer that would semi-automatically build functional units to perform whatever function the CPU was grinding on at the moment, with some sort of recognition engine and periodic updates garnered from participating customers to help special-yet-common cases. As well, seeing how customers actually use FPGA with their products will help Intel decide what functionality to add to their next (or next+1, etc) processor.
There are already options to add an FPGA to your Xeon system, with its own blob of RAM. Since they talk about this being fundamentally different, I'm not sure what makes sense except the idea of it being connected at the memory controller. Hopefully there will be a talk with some nice block diagrams released soon.
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Any way you set it up, your going to need OS support to reconfigure the FPGA. Perhaps a well defined section in the ELF format, with some kind of locking semantics to prevent more than one process from using it. That would depend on how many FPGA resources / CPU cores you have....
Anyone who is going to spend the money to buy and use these CPU's, will have to solve this problem. For the short term, this is likely to only be used in high end clustered server farms, for workloads where you wouldn't want to sw
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My guess would be this is for I/O.
These customers have lots of I/O that, if you can do high performance optimized operations on a general CPU how useful would that be ?
Think of something like liberouter or NetFFPGA embedded on the CPU die.
Or maybe the FPGA is used to implement calculations like crypto and hashes like CRC32C. Instead of building them into the silicon, why not make it possible to do research by loading new versions of it.
Maybe you just need to look around on the Internet what other companies
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It depends on what is connected to the FPGA, it could also be connected to the PCI-bus, but I guess you are right.
Re:Code (Score:4, Interesting)
LOL. But they will have to translate it to Verilog or VHDL, which is far harder.
I suppose it depends on your skill set, but I find Verilog to be much easier than coding GPU pipelines. You just need to realize that you are not coding a program that will be sequentially executed, but a hardware description where everything happens at once. Anyway, these chips sound really slick, and I would definitely pay for a PC containing a CPU with some FPGA fabric instead of a standard X86.
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LOL. But they will have to translate it to Verilog or VHDL, which is far harder.
I suppose it depends on your skill set, but I find Verilog to be much easier than coding GPU pipelines. You just need to realize that you are not coding a program that will be sequentially executed, but a hardware description where everything happens at once. Anyway, these chips sound really slick, and I would definitely pay for a PC containing a CPU with some FPGA fabric instead of a standard X86.
You don't have to close timing on an actual circuit when programming GPU. You write your program and off you go.
That is why programming an FPGA is way harder.
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>LOL. But they will have to translate it to Verilog or VHDL, which is far harder.
For you maybe. Some of us write synthesizable HDL all day and it's not hard at all.
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Yes but some applications, like High Frequency Trading focus solely on speed.
If this proves faster than GPU programming, I can see a lot of people heading in that direction...
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There are already network cards equipped with FPGAs to cut the latency down for such liquidity harvesting.
Making a general-purpose processor that people use where they used to use a bunch of custom kit is kind of intel's thing. Every so often they try making a specific-purpose processor and then they always return to generalization. This is pretty much the epitome of that trend, now they're not even telling you what the hardware will do.
This could be cool (Score:2)
*IF* its not some lame, slow, tiny array.. and if you get full access to it ( HDL or something )
what? (Score:3)
By using FPGAs to accelerate certain specific types of workloads, Intel Xeon customers can reap higher performance for critical functions without translating the majority of their code to OpenCL or bothering to update it for GPGPU.
What? This doesn't make sense. Unless Intel invented a way to automatically generate parallel code (in which case it could also be used in GPUs), somebody would have to rewrite the relevant parts of the program in VHDL, Verilog, OpenCL, or whatever.
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If you're paying $$ for custom Intel processors, you probably already have a way to leverage a particular function in parallel on the CPU
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I agree it is a good thing. IIRC, Altera even made a tool for synthesis from OpenCL (great for me, as I don't know VHDL and Verilog).
I'm in particular interested in that Parallella board (http://www.parallella.org/), but they're out of stock, and I've been the queue for months without a response.
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By using FPGAs to accelerate certain specific types of workloads, Intel Xeon customers can reap higher performance for critical functions without translating the majority of their code to OpenCL or bothering to update it for GPGPU.
What? This doesn't make sense. Unless Intel invented a way to automatically generate parallel code (in which case it could also be used in GPUs), somebody would have to rewrite the relevant parts of the program in VHDL, Verilog, OpenCL, or whatever.
I would assume the FPGA part of the CPU would be programmed in VHDL. Once programmed, it would act like a set of custom instruction sets in the CPU.
Simple example. An operation like a bit circling (10010 -> 00101 move the bits one step to the left and move the first bit to the end getting 00101) is very inefficient. You can left shift but the first bit falls of and then you have to and it and then put in the end. A lot of operations. A custom FPGA operation to do just that could be just one instruction
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I would assume the FPGA part of the CPU would be programmed in VHDL.
Yes, that's the obvious reasoning. And that's certainly interesting enough on its own. But the summary said
[...]for critical functions without translating the majority of their code[...]
Somebody has to do the translation, agree?
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It's called rotate, and MOST CPU's can do it.
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IMHO hardware design tools have had far less investment than compiler tools, and we're overdue to invest more effort in improving them.
Since the FPGA is in the CPU, I assume there are either CPU instructions to pipe data in and out of the FPGA. Or the FPGA may have direct access to the memory controller / cache. Either way you need a good way to synchronise between them.
So consider a solution that takes LLVM bitcode and runtime profiling data. Pick out some number of hot code blocks in an optimisation pas
OMG I WANT! (Score:2)
As a hardware hacker, god I want one of these. On chip reprogramable DSP!? While it's a niche market, I'd love to get my hands on some, and not have to give up my favorite OS or build custom boards to do signal processing.
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I tend to agree and will want one or 2 myself, but it still wont be quite as cool for hardware people, as you dont have any "programmable" pins hanging off this thing..
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Looks like you misspelled Stratix.
Actually the Virtex parts are faster (IO, at least) and larger, but Altera has OpenCL and. IMO, a much better toolchain than Xilinx. Xilinx has some awesome technology for 2.5D interposer hybrids which is bringing the scale up and the cost of scale down, but Altera has Intel 14nm trigate for their upcoming Stratix 10 parts, which may mean they are faster than Virtex 7.
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Perfect for High Frequency Trading platforms (Score:2)
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As a matter of policy, the feds of
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> pretend that keys longer than 56 bits don't exist!" theory of regulation is largely a relic.
But the law [gpo.gov] still sets a limit at 64 bits and requires you to get an export license for anything beyond.
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I have no doubt that the amount of paperwork require to fully comply with the law in exporting something every war3z kiddie in Iran already has is still silly, and I don't doubt that there's a cube somewhere in Intel Inc. whose salary is justi
Three Words (Score:3)
High-Frequency Trading
SoC, FPGA Development (Score:5, Interesting)
I have a friend in that in graduate school used a motherboard that could take an Altera FPGA in one of the Xeon sockets. This seems like the next logical step; hopefully it's not too expensive so that the hardware is accessible to hobbiest/engineers. I am happy that both Xilinx and Altera offer cheap development boards so that we can play with the new offerings. It's easier to convince a boss to use it if we're familiar with it. (hint hint, wry grin)
I use the zynq processor at my job, and am very happy with the amount of flexibility you can get out of an embedded system having access to the FPGA and processor fabric; you can directly access gigasample ADC's, etc. When I first got into embedded systems on an FPGA, the processor was a soft-IP and not terribly fast. Both Xilinx and Altera now offer ARM processors that run up to 1GHZ. The amount of system flexibility is great. You can make major architectural choices without changing the hardware. You might have a data-path, or computation that is simply too intensive for a processor to handle.. You have the flexibility to port this portion to the logic side. If you're in a rapid prototyping mode and are constrained by board size and mechanical packaging constraints, FPGAs are great.
Debugging SoC still has it's challenges though. It's easy to program FPGAs, and easy to program the microprocessor. The tools are still a little clunky from Xilinx or Altera to handle their hybrid SoC parts. There is still work to be done to make them work more seamlessly.
Custom hardware malware, factory direct to you (Score:3)
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Custom NSA snooper/decrypter, running at the hardware level.
what about the ram / pci-e lanes that are socket (Score:2)
what about the ram / pci-e lanes that are part of the socket?
Maybe in 4 way boards or some 2 socket boards.
2 socket broads can work with only 1 cpu. But what will they do when they see a filled socket but no ram and no PCI-E io?
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I don't know what you're talking about here
They're not selling FPGA's in an Intel socket. They're selling Xeon CPU's with integrated FPGA's.
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How can they be used for interconnects?
The CPU fits in the same socket an existing Xeons.
Looks more like a way to compete with AMD+GPU with just an Intel CPU.
This explains it (Score:2)
This explains why Intel was selling fab time to an FPGA vendor.
old timer here... (Score:2)
Image a Beowulf cluster of these!
Intel have done this before... and here's the snag (Score:4, Informative)
I'd already been thinking about the possibility of end-user-accessible, on-the-fly-reprogrammable FPGA functionality as part of a "regular" computer before I heard Intel had produced an integrated CPU/FPGA (though it's not clear how easily configurable the FPGA was there). I raised the issue in that previous thread and got a *very* interesting and informative response [slashdot.org] (thank you Tacvek) that pointed out some major problems with the concept of general access to such functionality.
The issues raised there explain why Intel are unlikely to be making an easily-reconfigurable hybrid product like this available to the general public any time soon, however smart and exciting the idea sounds.
Two words: (Score:2)
HF Trading (Score:2)
I bet HF trading ends up being a prime market for this technology.
Customer Instructions (Score:2)
Privacy? Yeah, we've heard of it. (Score:1)
"Bob, we're glad you Intel boys have finally come around".
"Hi Jeff. Yeah, well we just about got the marketing boys convinced enough to run with it. They managed to find an angle that flies pretty well. Gets us off the hook and gets your boys into a heck of a lot of servers!"
"Hey, it's a win-win so far as I'm concerned. Wish it could have been sooner though, but what with all this pressure from the purse-holders, we couldn't bankroll it for you".
"Times are getting tough, huh? It wasn't that long ago you NSA