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Hardware Technology

Tiny Chiplets: a New Level of Micro Manufacturing 83

concealment sends this quote from the NY Times: "Today’s chips are made on large wafers that hold hundreds of fingernail-sized dies, each with the same electronic circuit. The wafers are cut into individual dies and packaged separately, only to be reassembled on printed circuit boards, which may each hold dozens or hundreds of chips. PARC researchers have a very different model in mind. ... they have designed a laser-printer-like machine that will precisely place tens or even hundreds of thousands of chiplets, each no larger than a grain of sand, on a surface in exactly the right location and in the right orientation. The chiplets can be both microprocessors and computer memory as well as the other circuits needed to create complete computers. They can also be analog devices known as microelectromechanical systems, or MEMS, that perform tasks like sensing heat, pressure or motion. The new manufacturing system the PARC researchers envision could be used to build custom computers one at a time, or as part of a 3-D printing system that makes smart objects with computing woven right into them."
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Tiny Chiplets: a New Level of Micro Manufacturing

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  • They do put other things in chips besides just computer components

    • by kelemvor4 ( 1980226 ) on Tuesday April 09, 2013 @07:58PM (#43408033)
      I like cool ranch flavoring myself.
    • Yes, such things as salt, paprika flavor (or cheese and union). It makes for far more tasty chips.
    • by Guppy ( 12314 )

      They do put other things in chips besides just computer components

      This. ^

      I doubt you'll be seeing this on your desktop CPU, where everything can be banged out in the same fab. But suppose it were some telecom specialty chip, you could combine Silicon Carbide Chiplets with Germanium Chiplets with Laser Chiplets, all from different manufacturers.

  • of the weed they're smoking here at PARC in Palo Alto must be really good. It allows them to dream wide-open-eyed, glossing over showstoppers such as reliability and poor cost structure.

    What next? Tiny chiplet sections assembled to create tiny chiplets, then the ultimate goal of assembling components one atom at a time?

    • by Anonymous Coward

      There are already services like MOSIS to help low volume chip orders cut cost by essentially making a multi-tenent wafer in one fab run. Instead of having the customer buying a single prototype chip pay for a whole wafer's worth of processing, they each pay a part. It's like freight consolidators for container ships.

      A completely separate issue is processor-in-memory fab techniques. It turns out that the most efficient logic and RAM fabs use different physics to produce their electrical components on the

      • by girlinatrainingbra ( 2738457 ) on Tuesday April 09, 2013 @08:00PM (#43408053)
        re: unless they can also come up with an inkjet like process to change process chemistry on minute parts of the wafer, they will run into the same cost issues as all other process-in-memory researchers.
        I believe that the different substrates used in the printer are manufactured separately. E.G. printer well #1 contains thousands or millions of copies of chiplet-type #1, well #2 contains only 10^3s to 10^6s copies of chiplet-type #2, etc. So these "ink supplies" can all be manufactured separately, so a memory chiplet could be made on a wafer with process physics fine-tuned for RAM production, whereas a logic or multiplexing or signal-crossover chiplet could be made on a wafer using process physics tuned for logic LSI / VLSI production. Thus the individual ink types are manufactured in an optimal manner for the type of chiplet.
        It's when the chiplets are "sprayed" or distributed onto the final substrate that the lasers are used to reposition and realign and reorient the chiplets in order to combine them into a composite computational structure. Or that's my reading of TFA (un /. like of me to RTFA, but I did!)...
    • by Khyber ( 864651 )

      "What next? Tiny chiplet sections assembled to create tiny chiplets, then the ultimate goal of assembling components one atom at a time?"

      You mean similar to the already-existing multi-core technology used in GPUs?

      • by serbanp ( 139486 )

        Ahem, do you know how the multi-core GPU/whatever is made? All of the blocks sit nicely on the same die (except some MCM/stacked fancy stuff).

        The article talks about "printing" (i.e. placing) small dies onto a holding substrate, similar to present-day PCBs. This has obvious penalties regarding footprint, communication speed, manufacturability and cost of both "tiny chiplet" production (where large amounts of wafer area will be wasted on scribelines) and assembly/testing.

        A weird solution in search of a probl

  • It's still silicon (Score:5, Informative)

    by viperidaenz ( 2515578 ) on Tuesday April 09, 2013 @07:41PM (#43407937)

    TFA goes on to say it goes against 50 years of thinking. Spreading out transistors rather than putting them closer together.
    They're still placing traditionally produced silicon wafers on what is effectively a printed circuit board. The wafers are just smaller. The method of placing them is new.

    I don't see how spreading out parts of a system that operate in the many GHz range is going to help performance. You'll run into problems of electrons not passing charge quick enough because of that pesky speed of light thing. At 3GHz, light only travels 100mm per cycle. Electricity won't go further than 95mm in copper. Half that if you look at the speeds in parts of the core of old P4 processors, upwards of 7GHz.

    • I don't see how spreading out parts of a system that operate in the many GHz range is going to help performance. At 3GHz, light only travels 100mm per cycle.

      Presuming of course that the system operates in the many GHz range, or even needs to. Not to mention that you can pack a *bunch* of chiplets (each the size of a grain of sand and holding thousands of gates) in an area 100mm on a side.

    • by dissy ( 172727 )

      I don't see how spreading out parts of a system that operate in the many GHz range is going to help performance.

      But that is why they are doing this, to not spread them out like we are right now, to avoid the performance problems we have right now.

      In your computer, your CPU is in one package, the RAM in another, the GPU in another. They all attach to extremely long wires on a device known as a mother board.

      Instead of having one wafer with 1000 CPUs on it, broken apart and packaged in huge plastic boxes to be connected to other components over very long wires like we currently do, they will have one wafer with 1000 d

      • In my computer, virtually all the of high speed logic is in the CPU, bar the DRAM.
        The CPU, cache, GPU, memory controller, all on the same package. Like all desktop Intel CPU's.

        Intel/Micron already have a technology called "hybrid memory cube" that stacks silicon on top of each other in the same chip, so you can put ram on top of the cpu.

        NVidia are going to use it under the marketing term of "Stacked DRAM".

        A step behind this is "package on package" used in smartphones and the raspberrypi. The RAM chip is sol

    • It's all in the architecture. It looks like these systems could be effectively used to marry custom silicon to very high frequency cores produced using traditional techniques.

      Amazing stuff if it goes to production.

  • Wasn't Gene Amdahl trying to do this back in the late 70's? Yeah, thought so.
    • Well no. It's just multi-module packaging using a slightly odd chip placement technique. Getting a chip into a package that can safely be handled by a pick and place robot is a significant part of the expense in constructing chips. Packageless pick and place would seem like a valuable idea, and presumably fluids and magnetic fields can be more delicate than any mechanical robot. Pick and place all your chips "naked", then slap a lid on the result, and you can cram an entire motherboard worth of componen

      • They may even be able to build useful capacitors in the package. That is difficult with current lithographic processes, but if one could use more low precision layers one may be able to build a capacitor with more than a couple of pF of capacitance (and not too many of those pesky pH's). Slapping a couple of dozen low precision layers on a normal wafer would be difficult and expensive. Using this tech to assemble a chip after litho could mean useful in chip capacitors.
        In chip resistors could be improved
  • by Required Snark ( 1702878 ) on Tuesday April 09, 2013 @08:25PM (#43408193) []

    It has the same components as a traditional Xerox machine. There is a drum that rotates and their positioning technology put the chiplets in precise locations on the substrate. The chiplets are in a fluid that acts like toner.

    It appears that the performance depends on how fast the substrate conducts signals. At this point it seems unlikely that this is as fast as an on chip connection, but there seems to be no intrinsic reason that it would be any slower then the wires that hook a chip pad to a package pin. In aggregate the speed might be faster then a circuit board because the chiplits could be closer together then chips on a board.

    One possible deployment would be to use this to assemble components which are then packaged in a standard IC. It's like an SOIC, except the parts are not all on one piece of silicon.

    There are potential economies of scale. With an inventory of chiplets, and automation to make the interconnect substrate with CAD, a custom assembly line can create vast numbers of different configurations and not have to include a foundry in the loop.

    Despite all the naysayers that have already posted, this is a potentially game changing technology.

    • I'm having trouble seeing this as a viable manufacturing technique. How do you make the chiplets go down on the substrate in the desired orientation?
      • by Khyber ( 864651 )

        Same way reflow-soldering does it - surface tension, plus the possibility of two-way transistors and ICs.

      • That's why I posted a link to the patent application. In theory, if you post on Slashdot you should be smart enough to follow the link and be able to figure this out yourself.

        Here's an overview from the patent:

        The systems and methods described herein include in an example embodiment an electromechanical micro-assembler, described below, to fabricate a micro-assembly from a set of one or more micro-objects. An example fabrication process includes the following basic steps:1) encoding each micro-object with

    • Despite all the naysayers that have already posted, this is a potentially game changing technology.

      A game changer for whom?
      If it isn't fast, then it's going to be relegated to embedded applications.
      That may be a game changer for the embedded field, but your average consumer knows fuck all about embedded chips.

      • So why is this a game changer?
        Well its not yet but it could be...
        So basically we have to make small chips, this is because the parasitics decrease with size so we get more efficient as we get smaller (up to a point), we also get cheaper for simply geometric reasons (wafer/exposure area pretty much fixed cost) so yay more goodies from a chip.

        Tooling up is expensive and HARD, dude what do you mean a .032m lithography mask costs $500,000+ and it probably won't work perfectly for at least a couple of r

  • by Anonymous Coward

    And before our eyes, a new life form is born. 3D printers = "birth machines". As a mental exercise, factor in a number of years worth of Moore's law-driven enhancement of 3-D printer capabilities. Brave New World indeed...

The longer the title, the less important the job.