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Intel Hardware

TSMC and Global Foundries Plan Risky Process Jump As Intel Unveils 22nm SoC 60

MrSeb writes with news on the happenings with next generation fabrication processes. From the article: "... Intel's 22nm SoC unveil is important for a host of reasons. As process nodes shrink and more components move on-die, the characteristics of each new node have become particularly important. 22nm isn't a new node for Intel; it debuted the technology last year with Ivy Bridge, but SoCs are more complex than CPU designs and create their own set of challenges. Like its 22nm Ivy Bridge CPUs, the upcoming 22nm SoCs rely on Intel's Tri-Gate implementation of FinFET technology. According to Intel engineer Mark Bohr, the 3D transistor structure is the principle reason why the company's 22nm technology is as strong as it is. Earlier this year, we brought you news that Nvidia was deeply concerned about manufacturing economics and the relative strength of TSMC's sub-28nm planar roadmap. Morris Chang, TSMC's CEO, has since admitted that such concerns are valid, given that performance and power are only expected to increase by 20-25% as compared to 28nm. The challenge for both TSMC and GlobalFoundries is going to be how to match the performance of Intel's 22nm technology with their own 28nm products. 20nm looks like it won't be able to do so, which is why both companies are emphasizing their plans to move to 16nm/14nm ahead of schedule. There's some variation on which node comes next; both GlobalFoundries and Intel are talking up 14nm; TSMC is implying a quick jump to 16nm. Will it work? Unknown. TSMC and GlobalFoundries both have excellent engineers, but FinFET is a difficult technology to deploy. Ramping it up more quickly than expected while simultaneously bringing up a new process may be more difficult than either company anticipates."
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TSMC and Global Foundries Plan Risky Process Jump As Intel Unveils 22nm SoC

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  • by Tapewolf ( 1639955 ) on Tuesday December 11, 2012 @07:56AM (#42249318)

    I'm a bit scared of all this die shrinkage.

    We have lots of perfectly working gear around here older than most of our offspring...

    As transistor count goes up and feature size down can we expect more of our gear to start to go haywire over a shorter length of time or is there something baked into process steps to counteract or actually improve reliability?

    I'm not sure why this was modded down. Flash in particular has problems with smaller die sizes, and while lower longevity has certain economic benefits, environmentally it's a dead end.

    The other thing is the 11-year solar cycle... if we develop some ultra-high density technology during the low ebb, we may find that half our electronics get frazzled during the solar maximum.

People who go to conferences are the ones who shouldn't.